2024
Towards Automated Verification of Logarithmic Arithmetic.
CoRR, 2024
2022
CONTROL-CORE: A Framework for Simulation and Design of Closed-Loop Peripheral Neuromodulation Control Systems.
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IEEE Access, 2022
Towards Quantum Logarithm Number Systems.
Proceedings of the 29th IEEE Symposium on Computer Arithmetic, 2022
2020
Implementing the Residue Logarithmic Number System Using Interpolation and Cotransformation.
IEEE Trans. Computers, 2020
Training Neural Nets using only an Approximate Tableless LNS ALU.
Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020
2019
One-Hot Residue Logarithmic Number Systems.
Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019
Optimizing Mitchell's Method for Approximate Logarithmic Addition via Base Selection with Application to Back-Propagation.
Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019
Under- and Overflow Detection in the Residue Logarithmic Number System.
Proceedings of the 26th IEEE Symposium on Computer Arithmetic, 2019
2016
Guarding the guards: Enhancing LNS performance for common applications.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016
2014
Options for Denormal Representation in Logarithmic Arithmetic.
J. Signal Process. Syst., 2014
2013
Improved DNA-sticker arithmetic: tube-encoded-carry, Logarithmic Number System and Monte-Carlo methods.
Nat. Comput., 2013
Extending DNA-Sticker Arithmetic to Arbitrary Size Using Staples.
Proceedings of the DNA Computing and Molecular Programming - 19th International Conference, 2013
The Denormal Logarithmic Number System.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013
2011
A Real/Complex Logarithmic Number System ALU.
IEEE Trans. Computers, 2011
Configuring Field-Programmable Robot Arrays.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011
An Improved DNA-Sticker Addition Algorithm and Its Application to Logarithmic Arithmetic.
Proceedings of the DNA Computing and Molecular Programming - 17th International Conference, 2011
A Residue Logarithmic Number System ALU using interpolation and cotransformation.
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011
Towards a Quaternion Complex Logarithmic Number System.
Proceedings of the 20th IEEE Symposium on Computer Arithmetic, 2011
2010
A Novel Cotransformation for LNS Subtraction.
J. Signal Process. Syst., 2010
Bitstream Efficiency of Field Programmable One-Hot Arrays.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Dual-stylus-arm scratch drive micro-robots controlled by a communication channel.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Dual-stylus-arm scratch drive micro-robots controlled by an onboard parallax algorithm.
Proceedings of the IEEE International Conference on Robotics and Automation, 2010
Implementing LNS using filtering units of GPUs.
Proceedings of the IEEE International Conference on Acoustics, 2010
Low-voltage Scratch-drive Micro-scalpels Controlled by a Binary-encoded Signal.
Proceedings of the BIODEVICES 2010, 2010
2009
A System-on-a-Chip Implementation for Embedded Real-Time Model Predictive Control.
IEEE Trans. Control. Syst. Technol., 2009
Parallax-Docking and Reconfiguration of Field Programmable Robot Arrays Using an Intermittently-Powered One-Hot Controller.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009
Powering embedded CMOS logic on MEMS-based micro-robots.
Proceedings of the 2009 IEEE International Behavioral Modeling and Simulation Workshop, 2009
A Dual-Purpose Real/Complex Logarithmic Number System ALU.
Proceedings of the 19th IEEE Symposium on Computer Arithmetic, 2009
2007
Monte Carlo Logarithmic Number System for Model Predictive Control.
Proceedings of the FPL 2007, 2007
Cotransformation Provides Area and Accuracy Improvement in an HDL Library for LNS Subtraction.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007
A Serial Logarithmic Number System ALU.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007
LNS Subtraction Using Novel Cotransformation and/or Interpolation.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007
2006
Integer Multipliers with Overflow Detection.
IEEE Trans. Computers, 2006
A parallel search algorithm for CLNS addition optimization.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
A RISC Processor with Redundant LNS Instructions.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006
A co-processor FPGA platform for the implementation of real-time model predictive control.
Proceedings of the American Control Conference, 2006
2005
Using CLNS for FFTs in OFDM demodulation of UWB receivers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Hardware-based support vector machine classification in logarithmic number systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Approximating Trigonometric Functions with the Laws of Sines and Cosines using the Logarithmic Number System.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005
The Residue Logarithmic Number System: Theory and Implementation.
Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005
2004
Threshold Mean Larger Ratio Motion Estimation in MPEG Encoding Using LNS.
Proceedings of the Integrated Circuit and System Design, 2004
LPVIP: A Low-Power ROM-Less ALU for Low-Precision LNS.
Proceedings of the Integrated Circuit and System Design, 2004
Geometric-mean interpolation for logarithmic number systems.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Finite Precision Analysis of Support Vector Machine Classification in Logarithmic Number Systems.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004
LNS architectures for embedded model predictive control processors.
Proceedings of the 2004 International Conference on Compilers, 2004
2003
Fast Fourier Transforms Using the Complex Logarithmic Number System.
J. VLSI Signal Process., 2003
Error Analysis of the Kmetz/Maenner Algorithm.
J. VLSI Signal Process., 2003
Combined LNS Adder/Subtractors for DCT Hardware.
Proceedings of the First Workshop on Embedded Systems for Real-Time Multimedia, 2003
A VLIW Architecture for Logarithmic Arithmetic.
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003
Iterative Methods for Logarithmic Subtraction.
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003
The Interval Logarithmic Number System.
Proceedings of the 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 2003
2002
Reduced Power Consumption for MPEG Decoding with LNS.
Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002
Avoiding oddification to simplify MPEG-1 decoding with LNS.
Proceedings of the IEEE 5th Workshop on Multimedia Signal Processing, 2002
2001
A Single-Multiplier Quadratic Interpolator for LNS Arithmetic.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001
Design of a Faithful LNS Interpolator.
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001
Unrestricted Faithful Rounding is Good Enough for Some LNS Applications.
Proceedings of the 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 2001
1998
Arithmetic Co-Transformations in the Real and Complex Logarithmic Number Systems.
IEEE Trans. Computers, 1998
1997
On the cost effectiveness of logarithmic arithmetic for backpropagation training on SIMD processors.
Proceedings of International Conference on Neural Networks (ICNN'97), 1997
1992
Initializing RAM-based logarithmic processors.
J. VLSI Signal Process., 1992
Applying Features of IEEE 754 to Sign/Logarithm Arithmetic.
IEEE Trans. Computers, 1992
Comments on "An Architecture for Addition and Subtraction of Long Word Length Numbers in the Logarithmic Number System''.
IEEE Trans. Computers, 1992
1990
Redundant Logarithmic Arithmetic.
IEEE Trans. Computers, 1990
1989
Redundant logarithmic number systems.
Proceedings of the 9th Symposium on Computer Arithmetic, 1989
1988
Improved accuracy for logarithmic addition in DSP applications.
Proceedings of the IEEE International Conference on Acoustics, 1988
1981
A structured APL preprocessor.
ACM SIGPLAN Notices, 1981