An Efficient Short High-Order Non-Binary LDPC Decoder Architecture Using a Message-Adaptation EMS Algorithm.
IEEE Access, 2021
An Efficient High-Rate Non-Binary LDPC Decoder Architecture With Early Termination.
IEEE Access, 2019
Hardware-friendly LDPC Decoding Scheduling for 5G HARQ Applications.
Proceedings of the IEEE International Conference on Acoustics, 2019
A Shuffled-Based Iterative Demodulation and Decoding Scheme for Ldpc Coded Flash Memory.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018
An Efficient Combined Bit-Flipping and Stochastic LDPC Decoder Using Improved Probability Tracers.
IEEE Trans. Signal Process., 2017
Optimization Techniques for the Efficient Implementation of High-Rate Layered QC-LDPC Decoders.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
A 5.28-Gb/s LDPC Decoder With Time-Domain Signal Processing for IEEE 802.15.3c Applications.
IEEE J. Solid State Circuits, 2017
A modified gradient descent bit flipping decoding scheme for LDPC codes.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017
An IDD receiver of LDPC coded modulation scheme for flash memory applications.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
A 5.4 µW Soft-Decision BCH Decoder for Wireless Body Area Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
A low-complexity LDPC decoder for NAND flash applications.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014