VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative.
IEEE Trans. Very Large Scale Integr. Syst., 2022
SHA2 and SHA-3 accelerator design in a 7 nm technology within the European Processor Initiative.
Microprocess. Microsystems, November, 2021
CRFlex: A Flexible and Configurable Cryptographic Hardware Accelerator for AES Block Cipher Modes.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2021
Cryptographically Secure Pseudo-Random Number Generator IP-Core Based on SHA2 Algorithm.
Sensors, 2020
A simulated approach to evaluate side-channel attack countermeasures for the Advanced Encryption Standard.
Integr., 2019
Crypto Accelerators for Power-Efficient and Real-Time on-Chip Implementation of Secure Algorithms.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Empowering Deafblind Communication Capabilities by Means of AI-Based Body Parts Tracking and Remotely Controlled Robotic Arm for Sign Language Speakers.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019
Digital Random Number Generator Hardware Accelerator IP-Core for Security Applications.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019
A Simulated Approach to Evaluate Side Channel Attack Countermeasures for the Advanced Encryption Standard.
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018
Analysis of Cybersecurity Weakness in Automotive In-Vehicle Networking and Hardware Accelerators for Real-Time Cryptography.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2018