Physical-design-friendly hierarchical logic built-in self-test - A case study.
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Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.
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IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Hybrid Built-In Self-Test Architecture for Multi-port Static RAMs.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains.
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Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
A Measurement Device for the Dynamic Unbalance of Crankshaft.
Proceedings of the 2009 Pacific-Asia Conference on Circuits, Communications and Systems, 2009
Logic BIST Architecture for System-Level Test and Diagnosis.
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Proceedings of the Eighteentgh Asian Test Symposium, 2009
Practical Challenges in Logic BIST Implementation.
Proceedings of the 17th IEEE Asian Test Symposium, 2008