Specific ADC of NVM-Based Computation-in-Memory for Deep Neural Networks.
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IEEE Trans. Circuits Syst. I Regul. Pap., December, 2024
CoMN: Algorithm-Hardware Co-Design Platform for Nonvolatile Memory-Based Convolutional Neural Network Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2024
Low Quantization Error Readout Circuit with Fully Charge-Domain Calculation for Computation-in-Memory Deep Neural Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Pipeline Design of Nonvolatile-based Computing in Memory for Convolutional Neural Networks Inference Accelerators.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Co-optimization strategy between array operation and weight mapping for flash computing arrays to achieve high computing efficiency and accuracy.
Sci. China Inf. Sci., February, 2023
A Convolution Neural Network Accelerator Design with Weight Mapping and Pipeline Optimization.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Efficient Discrete Temporal Coding Spike-Driven In-Memory Computing Macro for Deep Neural Network Based on Nonvolatile Memory.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Novel Weight Mapping Method for Reliable NVM based Neural Network.
Proceedings of the IEEE International Reliability Physics Symposium, 2021
Decentralized adaptive output-feedback controller design for stochastic nonlinear interconnected systems.
Autom., 2012
Decentralized adaptive practical tracking of nonlinear interconnected systems with dynamic input and output interactions.
Proceedings of the 11th International Conference on Control, 2010
A clustering multi-objective evolutionary algorithm based on orthogonal and uniform design.
Proceedings of the IEEE Congress on Evolutionary Computation, 2009
A Novel Genetic Algorithm for Multi-criteria Minimum Spanning Tree Problem.
Proceedings of the Computational Intelligence and Security, International Conference, 2005