A 2-Bit 4-Level 4-Wire 56Gb/s Transceiver in 14nm FinFET.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
An 8-12GHz 0.92° Phase Error Quadrature Clock Generator Based on Two-Stage Poly Phase Filter with Intermediate Point Compensation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
An 8.52-11.34 GHz 0.34° Phase Error Quadrature Clock Generator with Time-Voltage-Time Convertor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A Sub-ps Integrated-Jitter 10 GHz ADPLL with Fractional Capacitor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A 108fs<sub>rms</sub> 0.45mW 100MS/s 1.25MHz bandwidth multi-bit ΔΣ time-to-digital converter with dynamic element matching.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A 40 Gb/s 74.9 mW PAM4 receiver with novel clock and data recovery.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
PAM4 receiver with adaptive threshold voltage and adaptive decision feedback equalizer.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016