Flip Point Offset-Compensation Sense Amplifier With Sensing-Margin-Enhancement for Dynamic Random-Access Memory.

A 9T-SRAM in-memory computing macro for Boolean logic and multiply-and-accumulate operations.

A note on scheduling on two identical machines with early work maximization.

A Pipeline Replica Bitline Technique for Suppressing Timing Variation of SRAM Sense Amplifiers in a 28-nm CMOS Process.

Read/write margin enhanced 10T SRAM for low voltage application.

Variation-resilient pipelined timing tracking circuit for SRAM sense amplifier.