A high-efficiency spaceborne processor for hybrid neural networks.
Neurocomputing, July, 2023
A Reconfigurable Neural Network Processor With Tile-Grained Multicore Pipeline for Object Detection on FPGA.
IEEE Trans. Very Large Scale Integr. Syst., 2021
Position-aware lightweight object detectors with depthwise separable convolutions.
J. Real Time Image Process., 2021
Hardware architecture design of HEVC entropy decoding.
Proceedings of the 2021 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom), New York City, NY, USA, September 30, 2021
Accuracy vs. Efficiency: Achieving both Through Hardware-Aware Quantization and Reconfigurable Architecture with Mixed Precision.
Proceedings of the 2021 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom), New York City, NY, USA, September 30, 2021
A Highly Efficient Heterogeneous Processor for SAR Imaging.
Sensors, 2019