2025
IEA-Plugin: An AI Agent Reasoner for Test Data Analytics.
CoRR, April, 2025
2024
Oracle-Checker Scheme for Evaluating a Generative Large Language Model.
CoRR, 2024
LLM-Assisted Analytics in Semiconductor Test (Invited).
Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024
WM-Graph: Graph-Based Approach for Wafermap Analytics.
Proceedings of the IEEE International Test Conference, 2024
2023
Domain Knowledge Graph Construction Via A Simple Checker.
CoRR, 2023
Welcome Message ITC 2023.
Proceedings of the IEEE International Test Conference, 2023
IEA-Plot: Conducting Wafer-Based Data Analytics Through Chat.
Proceedings of the IEEE International Test Conference, 2023
2022
Language Driven Analytics for Failure Pattern Feedforward and Feedback.
Proceedings of the IEEE International Test Conference, 2022
Wafer Map Pattern Analytics Driven By Natural Language Queries.
Proceedings of the IEEE International Test Conference in Asia, 2022
2021
MINiature Interactive Offset Networks (MINIONs) for Wafer Map Classification.
Proceedings of the IEEE International Test Conference, 2021
2020
Learning A Wafer Feature With One Training Sample.
Proceedings of the IEEE International Test Conference, 2020
2019
Wafer Pattern Recognition Using Tucker Decomposition.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019
Primitive Concept Identification In A Given Set Of Wafer Maps.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019
Deploying A Machine Learning Solution As A Surrogate.
Proceedings of the IEEE International Test Conference, 2019
Wafer Plot Classification Using Neural Networks and Tensor Methods.
Proceedings of the IEEE International Test Conference in Asia, 2019
Facilitating Deployment Of A Wafer-Based Analytic Software Using Tensor Methods: Invited Paper.
Proceedings of the International Conference on Computer-Aided Design, 2019
2018
Discovering Interesting Plots in Production Yield Data Analytics.
CoRR, 2018
A Concept Learning Tool Based On Calculating Version Space Cardinality.
CoRR, 2018
Special session on machine learning for test and diagnosis.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
An Autonomous System View To Apply Machine Learning.
Proceedings of the IEEE International Test Conference, 2018
Concept Recognition in Production Yield Data Analytics.
Proceedings of the IEEE International Test Conference, 2018
Machine Learning for Feature-Based Analytics.
Proceedings of the 2018 International Symposium on Physical Design, 2018
2017
Experience of Data Analytics in EDA and Test - Principles, Promises, and Challenges.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Challenges and Trends in Modern SoC Design Verification.
IEEE Des. Test, 2017
Data-Driven Test Plan Augmentation for Platform Verification.
IEEE Des. Test, 2017
Guest Editors' Introduction: Emerging Challenges and Solutions in SoC Verification.
IEEE Des. Test, 2017
Learning the process for correlation analysis.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017
Dynamic Exerciser Template Weighting in x86 Processor Verification.
Proceedings of the 18th International Workshop on Microprocessor and SOC Test and Verification, 2017
Some considerations on choosing an outlier method for automotive product lines.
Proceedings of the IEEE International Test Conference, 2017
Kernel based clustering for quality improvement and excursion detection.
Proceedings of the IEEE International Test Conference, 2017
Systematic defect detection methodology for volume diagnosis: A data mining perspective.
Proceedings of the IEEE International Test Conference, 2017
Learning to Produce Direct Tests for Security Verification Using Constrained Process Discovery.
Proceedings of the 54th Annual Design Automation Conference, 2017
Feature extraction from design documents to enable rule learning for improving assertion coverage.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
ITC and the Future of Test - We've Won.
IEEE Des. Test, 2016
Consistency in wafer based outlier screening.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Session 4B - Panel data analytics in semiconductor manufacturing.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
2015
Generalization of an outlier model into a "global" perspective.
Proceedings of the 2015 IEEE International Test Conference, 2015
Machine Learning in Simulation-Based Analysis.
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015
Data mining in functional test content optimization.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
Design trends and test challenges in automotive electronics.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
Yield optimization using advanced statistical correlation methods.
Proceedings of the 2014 International Test Conference, 2014
Multivariate outlier modeling for capturing customer returns - How simple it can be.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
On application of data mining in functional debug.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014
Data Mining In EDA - Basic Principles, Promises, and Constraints.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
Guest Editorial: Test and Verification Challenges for Future Microprocessors and SoC Designs.
J. Electron. Test., 2013
Novel test analysis to improve structural coverage - A commercial experiment.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013
Analyzing Efficacy of Constrained Test Program Generators - A Case Study.
Proceedings of the 14th International Workshop on Microprocessor Test and Verification, 2013
A pattern mining framework for inter-wafer abnormality analysis.
Proceedings of the 2013 IEEE International Test Conference, 2013
Data mining in design and test processes: basic principles and promises.
Proceedings of the International Symposium on Physical Design, 2013
Simulation knowledge extraction and reuse in constrained random processor verification.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
Introduction to special section on verification challenges in the concurrent world.
ACM Trans. Design Autom. Electr. Syst., 2012
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
Data mining based prediction paradigm and its applications in design automation.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
An experiment of burn-in time reduction based on parametric test analysis.
Proceedings of the 2012 IEEE International Test Conference, 2012
Screening customer returns with multivariate test analysis.
Proceedings of the 2012 IEEE International Test Conference, 2012
Functional test content optimization for peak-power validation - An experimental study.
Proceedings of the 2012 IEEE International Test Conference, 2012
Novel test detection to improve simulation efficiency - A commercial experiment.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
2011
Understanding customer returns from a test perspective.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011
Forward prediction based on wafer sort data - A case study.
Proceedings of the 2011 IEEE International Test Conference, 2011
Multidimensional parametric test set optimization of wafer probe data for predicting in field failures and setting tighter test limits.
Proceedings of the Design, Automation and Test in Europe, 2011
2010
Increasing the Efficiency of Simulation-Based Functional Verification Through Unsupervised Support Vector Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Feature-Ranking Methodology to Diagnose Design-Silicon Timing Mismatch.
IEEE Des. Test Comput., 2010
Impact of multiple input switching on delay test under process variation.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Selecting the most relevant structural Fmax for system Fmax correlation.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Mining AC delay measurements for understanding speed-limiting paths.
Proceedings of the 2011 IEEE International Test Conference, 2010
A kernel-based approach for functional test program generation.
Proceedings of the 2011 IEEE International Test Conference, 2010
On evaluating speed path detection of structural tests.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Analog behavioral modeling flow using statistical learning method.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
A non-parametric approach to behavioral device modeling.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
A new sampling method for analog behavioral modeling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Online selection of effective functional test programs based on novelty detection.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Classification rule learning using subgroup discovery of cross-domain attributes responsible for design-silicon mismatch.
Proceedings of the 47th Design Automation Conference, 2010
Data learning based diagnosis.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
Correlating system test Fmax with structural test Fmax and process monitoring measurements.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
Automatic assertion extraction via sequential data mining of simulation traces.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
A Statistical Diagnosis Approach for Analyzing Design-Silicon Timing Mismatch.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Minimizing outlier delay test cost in the presence of systematic variability.
Proceedings of the 2009 IEEE International Test Conference, 2009
Data learning techniques and methodology for Fmax prediction.
Proceedings of the 2009 IEEE International Test Conference, 2009
Feature based similarity search with application to speedpath analysis.
Proceedings of the 2009 IEEE International Test Conference, 2009
Data Learning Techniques for Functional/System Fmax Prediction.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
Predicting variability in nanoscale lithography processes.
Proceedings of the 46th Design Automation Conference, 2009
Speedpath analysis based on hypothesis pruning and ranking.
Proceedings of the 46th Design Automation Conference, 2009
Path selection for monitoring unexpected systematic timing effects.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
A Clock-Less Jitter Spectral Analysis Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
Linking Statistical Learning to Diagnosis.
IEEE Des. Test Comput., 2008
A Study of Outlier Analysis Techniques for Delay Testing.
Proceedings of the 2008 IEEE International Test Conference, 2008
Diagnosis of design-silicon timing mismatch with feature encoding and importance ranking - the methodology explained.
Proceedings of the 2008 IEEE International Test Conference, 2008
Functional test selection based on unsupervised support vector analysis.
Proceedings of the 45th Design Automation Conference, 2008
Speedpath prediction based on learning from a small set of examples.
Proceedings of the 45th Design Automation Conference, 2008
Statistical diagnosis of unmodeled systematic timing effects.
Proceedings of the 45th Design Automation Conference, 2008
Refining Delay Test Methodology Using Knowledge of Asymmetric Transition Delay.
Proceedings of the 17th IEEE Asian Test Symposium, 2008
2007
A Survey of Hybrid Techniques for Functional Verification.
IEEE Des. Test Comput., 2007
Guest Editors' Introduction: Attacking Functional Verification through Hybrid Techniques.
IEEE Des. Test Comput., 2007
Statistical analysis and optimization of parametric delay test.
Proceedings of the 2007 IEEE International Test Conference, 2007
Enhancing signal controllability in functional test-benches through automatic constraint extraction.
Proceedings of the 2007 IEEE International Test Conference, 2007
Analyzing the risk of timing modeling based on path delay tests.
Proceedings of the 2007 IEEE International Test Conference, 2007
An incremental learning framework for estimating signal controllability in unit-level verification.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Coverage-directed test generation through automatic constraint extraction.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007
Design-Silicon Timing Correlation A Data Mining Perspective.
Proceedings of the 44th Design Automation Conference, 2007
2006
Simulation-Based Functional Test Generation for Embedded Processors.
IEEE Trans. Computers, 2006
Issues on Test Optimization with Known Good Dies and Known Defective Dies - A Statistical Perspective.
Proceedings of the 2006 IEEE International Test Conference, 2006
An Efficient Pruning Method to Guide the Search of Precision Tests in Statistical Timing Space.
Proceedings of the 2006 IEEE International Test Conference, 2006
Simulation-based functional test justification using a decision-digram-based Boolean data miner.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006
On bounding the delay of a critical path.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Extracting a Simplified View of Design Functionality Based on Vector Simulation.
Proceedings of the Hardware and Software, 2006
Extracting a simplified view of design functionality via vector simulation.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006
Refined statistical static timing analysis through.
Proceedings of the 43rd Design Automation Conference, 2006
2005
Using 2-domain partitioned OBDD data structure in an enhanced symbolic simulator.
ACM Trans. Design Autom. Electr. Syst., 2005
On A Software-Based Self-Test Methodology and Its Application.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005
On Silicon-Based Speed Path Identification.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005
Reducing Pattern Delay Variations for Screening Frequency Dependent Defects.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005
Simulation Data Mining for Functional Test Pattern Justification.
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005
Simulation-based target test generation techniques for improving the robustness of a software-based-self-test methodology.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
Hazard-aware statistical timing simulation and its applications in screening frequency-dependent defects.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
On Generating Tests to Cover Diverse Worst-Case Timing Corners.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
An Efficient Sequential SAT Solver With Improved Search Strategies.
Proceedings of the 2005 Design, 2005
2004
A new sigma-delta modulator architecture for testing using digital stimulus.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
Critical path selection for delay fault testing based upon a statistical timing model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
Multilevel circuit clustering for delay minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
A Signal Correlation Guided Circuit-SAT Solver.
J. Univers. Comput. Sci., 2004
Safety Property Verification Using Sequential SAT and Bounded Model Checking.
IEEE Des. Test Comput., 2004
New Challenges in Delay Testing of Nanometer, Multigigahertz Designs.
IEEE Des. Test Comput., 2004
Guest Editors' Introduction: The Verification and Test of Complex Digital ICs.
IEEE Des. Test Comput., 2004
A Scalable On-Chip Jitter Extraction Technique.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004
On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design.
Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004
On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
Static statistical timing analysis for latch-based pipeline designs.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
A path-based methodology for post-silicon timing validation.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
On using a 2-domain partitioned OBDD data structure in verification.
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004
Regression Simulation: Applying Path-Based Learning In Delay Test and Post-Silicon Validation.
Proceedings of the 2004 Design, 2004
Random Jitter Extraction Technique in a Multi-Gigahertz Signal.
Proceedings of the 2004 Design, 2004
Pattern Selection for Testing of Deep Sub-Micron Timing Defects.
Proceedings of the 2004 Design, 2004
Improved Symoblic Simulation by Dynamic Funtional Space Partitioning.
Proceedings of the 2004 Design, 2004
On path-based learning and its applications in delay test and diagnosis.
Proceedings of the 41th Design Automation Conference, 2004
An efficient finite-domain constraint solver for circuits.
Proceedings of the 41th Design Automation Conference, 2004
TranGen: a SAT-based ATPG for path-oriented transition faults.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Efficient reachability checking using sequential SAT.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Jitter spectral extraction for multi-gigahertz signal.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Improved symbolic simulation by functional-space decomposition.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
Critical Path Selection for Deep Sub-Micron Delay Test and Timing Validation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
Guest Editors' Introduction: Speed Test and Speed Binning for Complex ICs.
IEEE Des. Test Comput., 2003
Enhanced Symbolic Simulation for Functional Verification of Embedded Array Systems.
Des. Autom. Embed. Syst., 2003
Diagnosis of Delay Defects Using Statistical Timing Models.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003
Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
On Structural vs. Functional Testing for Delay Faults.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003
A comparison of BDDs, BMC, and sequential SAT for model checking.
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003
A Circuit SAT Solver With Signal Correlation Guided Learning.
Proceedings of the 2003 Design, 2003
Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step.
Proceedings of the 2003 Design, 2003
A signal correlation guided ATPG solver and its applications for solving difficult industrial cases.
Proceedings of the 40th Design Automation Conference, 2003
Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models.
Proceedings of the 40th Design Automation Conference, 2003
Delta-sigma modulator based mixed-signal BIST architecture for SoC.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
Experience in critical path selection for deep sub-micron delay test and timing validation.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
Enhanced symbolic simulation for efficient verification of embedded array systems.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2002
Validation and Verification of Complex Digital Systems: A Practical Perspective.
Proceedings of the 3rd Latin American Test Workshop, 2002
On Testing High-Performance Custom Circuits without Explicit Testing of the Internal Faults.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
On theoretical and practical considerations of path selection for delay fault testing.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002
Fortuitous Detection and its Impact on Test Set Sizes Using Stuck-at and Transition Faults.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002
Enhancing test efficiency for delay fault testing using multiple-clocked schemes.
Proceedings of the 39th Design Automation Conference, 2002
False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation.
Proceedings of the 39th Design Automation Conference, 2002
2001
Defect-Oriented Testing and Defective-Part-Level Prediction.
IEEE Des. Test Comput., 2001
Analysis of Testing Methodologies for Custom Designs in PowerPCTM Microprocessor.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001
Verification and Validation of Complex Digital Systems: An Industrial Perspective.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001
Module placement with boundary constraints using the sequence-pair representation.
Proceedings of ASP-DAC 2001, 2001
2000
On Efficiently Producing Quality Tests for Custom Circuits in PowerPC<sup>TM</sup> Microprocessors.
J. Electron. Test., 2000
Enhanced DO-RE-ME based defect level prediction using defect site aggregation-MPG-D.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000
On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000
Collaboration between Industry and Academia in Test Research.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000
1999
Experience in Validation of PowerPCTM Microprocessor Embedded Arrays.
J. Electron. Test., 1999
REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experimen.
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Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999
Tradeoff analysis for producing high quality tests for custom circuits in PowerPC microprocessors.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999
Modeling the probability of defect excitation for a commercial IC with implications for stuck-at fault-based ATPG strategies.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999
1998
On measuring the effectiveness of various design validation approaches for PowerPC microprocessor embedded arrays.
ACM Trans. Design Autom. Electr. Syst., 1998
Test Generation Based on High-Level Assertion Specification for PowerPCTM Microprocessor Embedded Arrays.
J. Electron. Test., 1998
On Logic and Transistor Level Design Error Detection of Various Validation Approaches for PowerPC(tm) Microprocessor Arrays.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998
Practical Considerations in Formal Equivalence Checking of PowerPC(tm) Microprocessors.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998
Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor Arrays.
Proceedings of the 1998 Design, 1998
Automatic Generation of Assertions for Formal Verification of PowerPC Microprocessor Arrays Using Symbolic Trajectory Evaluation.
Proceedings of the 35th Conference on Design Automation, 1998
1997
A New Validation Methodology Combining Test and Formal Verification for PowerPC<sup>TM</sup> Microprocessor Arrays.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997
1996
Using Target Faults To Detect Non-Tartget Defects.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996
A Better ATPG Algorithm and Its Design Principles.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996
1995
On the decline of testing efficiency as fault coverage approaches 100%.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995
On Efficiently and Reliably Achieving Low Defective Part Levels.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995
Enhanced testing performance via unbiased test sets.
Proceedings of the 1995 European Design and Test Conference, 1995
1993
Experience in Massively Parallel Discrete Event Simulation.
Proceedings of the 5th Annual ACM Symposium on Parallel Algorithms and Architectures, 1993
1991
Parallel algorithm and complexity results for telephone link simulation.
Proceedings of the Third IEEE Symposium on Parallel and Distributed Processing, 1991