18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution.
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM).
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
A 512 Mb Two-Channel Mobile DRAM (OneDRAM) With Shared Memory Array.
,
,
,
,
,
,
,
,
,
,
,
,
,
,
IEEE J. Solid State Circuits, 2008