2024
De-Correlation and De-Bias Post-Processing Circuits for True Random Number Generator.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2024

A 0.116 pJ/bit Latch-Based True Random Number Generator Featuring Static Inverter Selection and Noise Enhancement.
IEEE Trans. Very Large Scale Integr. Syst., March, 2024

A 0.9-2.6pW 0.1-0.25V 22nm 2-bit Supply-to-Digital Converter Using Always-Activated Supply-Controlled Oscillator and Supply-Dependent-Activation Buffers for Bio-Fuel-Cell-Powered-and-Sensed Time-Stamped Bio-Recording.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

A 2 Hz, 1.2-2 V, 0.22-9 nW, 0.007 mm<sup>2</sup> 65 nm CMOS Multiple- Output Down-Converter-Less Clock Generator Using Stacked an Oscillator and Frequency Dividers for Scaling-Friendly IoTs.
Proceedings of the 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024

A 0.00027 mm<sup>2</sup> 1.2V 0.089pJ/bit 10Gbps 41.6 GHz Standard-Cell-Based Passive-Less Wireless OOK Transmitter with On-Chip Antenna in 12nm FinFET.
Proceedings of the 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024

CLAPPER: Clonable LFSR-based Asymmetric PUF-group with Peer-to-peer Equivalent Response.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

2023
Practical Markov Chain and Von Neumann based Post-processing Circuits for True Random Number Generators.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

A 100-Bit-Output Modeling Attack-Resistant SPN Strong PUF with Uniform and High-Randomness Response.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022
A 0.186-pJ per Bit Latch-Based True Random Number Generator Featuring Mismatch Compensation and Random Noise Enhancement.
IEEE J. Solid State Circuits, 2022

A 0.116pJ/bit Latch-Based True Random Number Generator with Static Inverter Selection and Noise Enhancement.
Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022

A 2.17-pJ/b 5b-Response Attack-Resistant Strong PUF with Enhanced Statistical Performance.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2021
A 0.5-V Hybrid SRAM Physically Unclonable Function Using Hot Carrier Injection Burn-In for Stability Reinforcement.
IEEE J. Solid State Circuits, 2021

A 0.186-pJ per Bit Latch-Based True Random Number Generator with Mismatch Compensation and Random Noise Enhancement.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

36.3 A Modeling Attack Resilient Strong PUF with Feedback-SPN Structure Having <0.73% Bit Error Rate Through In-Cell Hot-Carrier Injection Burn-In.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
A 373-F<sup>2</sup> 0.21%-Native-BER EE SRAM Physically Unclonable Function With 2-D Power-Gated Bit Cells and ${V}_{\text{SS}}$ Bias-Based Dark-Bit Detection.
IEEE J. Solid State Circuits, 2020

An Inverter-Based True Random Number Generator with 4-bit Von-Neumann Post-Processing Circuit.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

A 0.5-V 2.07-fJ/b 497-F<sup>2</sup> EE/CMOS Hybrid SRAM Physically Unclonable Function with < 1E-7 Bit Error Rate Achieved through Hot Carrier Injection Burn-in.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2018
A 373 F<sup>2</sup> 2D Power-Gated EE SRAM Physically Unclonable Function With Dark-Bit Detection Technique.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018