Tuning the continual flow pipeline architecture with virtual register renaming.
ACM Trans. Archit. Code Optim., 2014
Tuning the continual flow pipeline architecture.
Proceedings of the International Conference on Supercomputing, 2013
Virtual register renaming: energy efficient substrate for continual flow pipelines.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
Streamlining the continual flow processor architecture with fast replay loop.
Proceedings of Eurocon 2013, 2013
Disjoint out-of-order execution processor.
ACM Trans. Archit. Code Optim., 2012
Simultaneous continual flow pipeline architecture.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
On the potential of latency tolerant execution in speculative multithreading.
Proceedings of the 1st international forum on Next-generation multicore/manycore technologies, 2008
A simple latency tolerant processor.
Proceedings of the 26th International Conference on Computer Design, 2008