A Rail-to-Rail 12 MS/s 91.3 dB SNDR 94.1 dB DR Two-Step SAR ADC With Integrated Input Buffer Using Predictive Level-Shifting.
IEEE J. Solid State Circuits, December, 2023
A Rail-to-Rail 12MS 91.3dB SNDR 94.1dB DR Two-Step SAR ADC with Integrated Input Buffer Using Predictive Level-Shifting.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A Hybrid Continuous Time Incremental and SAR Two-Step ADC with 90.5dB DR over 1MHz BW.
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Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
LMS-Based Noise Leakage Calibration of Cascaded Continuous-Time Delta Sigma Modulators.
IEEE J. Solid State Circuits, 2010
A Fifth-Order G<sub>m</sub>-C Continuous-Time ΔΣ Modulator With Process-Insensitive Input Linear Range.
IEEE J. Solid State Circuits, 2009
A self-calibrated 2-1-1 cascaded continuous-time ΔΣ modulator.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
A CMOS 1×-16× speed DVD write channel IC.
IEEE J. Solid State Circuits, 2006