Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Cost-Effective Error Detection Through Mersenne Modulo Shadow Datapaths.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Low-cost hardware architectures for mersenne modulo functional units.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
Robust and reliable hardware accelerator design through high-level synthesis
PhD thesis, 2017
New advances of high-level synthesis for efficient and reliable hardware design.
Integr., 2017
Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights.
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Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Designing high-quality hardware on a development effort budget: A study of the current state of high-level synthesis.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
High-level Synthesis for Low-power Design.
IPSJ Trans. Syst. LSI Des. Methodol., 2015
High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths.
Proceedings of the 52nd Annual Design Automation Conference, 2015
Hybrid quick error detection (H-QED): accelerator validation and debug using high-level synthesis principles.
Proceedings of the 52nd Annual Design Automation Conference, 2015