7.1 A low-power 64Gb MLC NAND-flash memory in 15nm CMOS technology.
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Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
A 12 MHz data cycle 4 Mb DRAM with pipeline operation.
IEEE J. Solid State Circuits, April, 1991
A latch-up-like new failure mechanism for high-density CMOS dynamic RAMs.
IEEE J. Solid State Circuits, February, 1990
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IEEE J. Solid State Circuits, April, 1989