Design of Delay-Insensitive Three Dimension Pipeline Array Multiplier for Image Processing.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002
Checking Delay-Insensitivity: 10<sup>4</sup> Gates and Beyond.
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002
Asynchronous Design Using Commercial HDL Synthesis Tools.
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000
An Asynchronous 2-D Discrete Cosine Transform Chip.
Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March, 1998