2013
Dynamic On-Chip Thermal Optimization for Three-Dimensional Networks-On-Chip.
Comput. J., 2013
2011
Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network.
IEEE Trans. Ind. Electron., 2011
Cycle avoidance in 2D/3D bidirectional graphs using shortest-path dynamic programming network.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Comparative ODE benchmarking of unidirectional and bidirectional DP networks for 3D-IC.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
On-chip dynamic programming networks using 3D-TSV integration.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011
2010
A CMOS Current-Mode Dynamic Programming Circuit.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
2009
Intra-daily information of range-based volatility for MEM-GARCH.
Math. Comput. Simul., 2009
A DP-network for optimal dynamic routing in network-on-chip.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009
2007
A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing.
Proceedings of the First International Symposium on Networks-on-Chips, 2007
A Current-Mode Analog Circuit for Reinforcement Learning Problems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
How Does Sample Size Affect GARCH Models?
Proceedings of the 2006 Joint Conference on Information Sciences, 2006
2004
An ICA design of intraday stock prediction models with automatic variable selection.
Proceedings of the IEEE International Joint Conference on Neural Networks, 2004
On Computing Maximum Likelihood Phylogeny Using FPGA p.
Proceedings of the Field Programmable Logic and Application, 2004
FPGA-Based Computation for Maximum Likelihood Phylogenetic Tree Evaluation.
Proceedings of the Field Programmable Logic and Application, 2004
Embedded Computation of Maximum-Likelihood Phylogeny Inference Using Platform FPGA.
Proceedings of the 3rd International IEEE Computer Society Computational Systems Bioinformatics Conference, 2004
2003
Analog and digital FPGA implementation of BRIN for optimization problems.
IEEE Trans. Neural Networks, 2003
Field programmable gate arrays and analog implementation of BRIN for optimization problems.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
An FPGA-based eigenfilter using fast Hebbian learning.
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003
High Speed GAML-based Phylogenetic Tree Reconstruction Using HW/SW Codesign.
Proceedings of the 2nd IEEE Computer Society Bioinformatics Conference, 2003
2002
Extracting Causation Knowledge from Natural Language Texts.
Proceedings of the Advances in Knowledge Discovery and Data Mining, 2002
Serial-parallel tradeoff analysis of all-pairs shortest path algorithms in reconfigurable computing.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002
On Computing Transitive-Closure Equivalence Sets Using a Hybrid GA-DP Approach.
Proceedings of the Field-Programmable Logic and Applications, 2002
1996
A binary relation inference network Part 1. General concepts.
Int. J. Syst. Sci., 1996
A continuous-time inference network and its hybrid implementations.
Int. J. Syst. Sci., 1996
A binary relation inference network Part 2. State-space techniques.
Int. J. Syst. Sci., 1996
1993
Digital Circuit Implementation of a Continuous-time Inference Network for the Transitive Closure Problem.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
1991
On a Binary Relation Inference Network.
Proceedings of the Fifth International Parallel Processing Symposium, Proceedings, Anaheim, California, USA, April 30, 1991