Exploring unified biometrics with encoded dictionary for hardware security of fault secured IP core designs.
Comput. Electr. Eng., October, 2023
Quadruple phase watermarking during high level synthesis for securing reusable hardware intellectual property cores.
Comput. Electr. Eng., January, 2023
Designing Low Cost Secured DSP Core using Steganography and PSO for CE systems.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022
Asynchronous 1R-1W dual-port SRAM by using single-port SRAM in 28nm UTBB-FDSOI technology.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
Quantification of figures of merit of 7T and 8T SRAM cells in subthreshold region and their comparison with the conventional 6T SRAM cell.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016