Component Dependencies Based Network-on-Chip Test.
IEEE Trans. Computers, December, 2024
An efficient tree-topological local mesh refinement on Cartesian grids for multiple moving objects in incompressible flow.
J. Comput. Phys., April, 2023
ECDR$^{2}$2: Error Corrector and Detector Relocation Router for Network-on-Chip.
IEEE Trans. Computers, 2021
Efficient Design-for-Test Approach for Networks-on-Chip.
IEEE Trans. Computers, 2019
Optimized mapping algorithm to extend lifetime of both NoC and cores in many-core system.
Integr., 2019
Testing aware dynamic mapping for path-centric network-on-chip test.
Integr., 2019
Online Path-Based Test Method for Network-on-Chip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Micro-Architecture Design for Low Overhead Fault Tolerant Network-on-Chip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Optimizing dynamic mapping techniques for on-line NoC test.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
A lifetime-aware mapping algorithm to extend MTTF of Networks-on-Chip.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
Minimizing the system impact of router faults by means of reconfiguration and adaptive routing.
Microprocess. Microsystems, 2017
Non-blocking BIST for continuous reliability monitoring of Networks-on-Chip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
A low latency fault tolerant transmission mechanism for Network-on-Chip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Non-Blocking Testing for Network-on-Chip.
IEEE Trans. Computers, 2016
VisualNoC: A Visualization and Evaluation Environment for Simulation and Mapping.
Proceedings of the Fourth ACM International Workshop on Many-core Embedded Systems, 2016
Optimizing the location of ECC protection in network-on-chip.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016
WeNA: Deterministic Run-time Task Mapping for Performance Improvement in Many-core Embedded Systems.
IEEE Embed. Syst. Lett., 2015
Design of Fault-Tolerant and Reliable Networks-on-Chip.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Rescuing healthy cores against disabled routers.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
A Fault-Tolerant Routing Algorithm for NoC Using Farthest Reachable Routers.
Proceedings of the IEEE 11th International Conference on Dependable, 2013