2025
Case Study: AI-Driven Log Extraction and Trace Outlier Detection for Efficient Post-Silicon Validation.
Proceedings of the 26th IEEE Latin American Test Symposium, 2025
2024
Subnetwork Based Traffic Aware Rerouting for CMesh Bufferless Network-on-Chip.
J. Circuits Syst. Comput., August, 2024
Sec-NoC: A Lightweight Secure Communication System for On-Chip Interconnects.
IEEE Embed. Syst. Lett., June, 2024
Enhancing Lifetime and Performance of MLC NVM Caches Using Embedded Trace Buffers.
ACM Trans. Design Autom. Electr. Syst., May, 2024
TROP: TRust-aware OPportunistic Routing in NoC with Hardware Trojans.
ACM Trans. Design Autom. Electr. Syst., March, 2024
DRackSim: Simulating CXL-enabled Large-Scale Disaggregated Memory Systems.
Proceedings of the 38th ACM SIGSIM Conference on Principles of Advanced Discrete Simulation, 2024
COPAR: Coordinated Packet Rerouting Attacks in NoC.
Proceedings of the 12th International Conference on Intelligent Systems and Embedded Design, 2024
Handling Packet Blocking Attack in NoC Using Traffic Snooping.
Proceedings of the IEEE International Conference on Omni-layer Intelligent Systems, 2024
2023
ELEMENT: Energy-Efficient Multi-NoP Architecture for IMC-Based 2.5-D Accelerator for DNN Training.
IEEE Des. Test, December, 2023
Self Adaptive Logical Split Cache Techniques for Delayed Aging of NVM LLC.
ACM Trans. Design Autom. Electr. Syst., November, 2023
Secure Routing Framework for Mitigating Time-Delay Trojan Attack in System-on-Chip.
J. Syst. Archit., November, 2023
ZPP: A Dynamic Technique to Eliminate Cache Pollution in NoC based MPSoCs.
ACM Trans. Embed. Comput. Syst., October, 2023
Modelling and Impact Analysis of Antipode Attack in Bufferless On-Chip Networks.
SN Comput. Sci., May, 2023
DRackSim: Simulator for Rack-scale Memory Disaggregation.
CoRR, 2023
Strengthening NoC Security: Leveraging Hybrid Encryption for Data Packet Protection.
Proceedings of the IEEE Region 10 Conference, 2023
A Practical Approach For Workload-Aware Data Movement in Disaggregated Memory Systems.
Proceedings of the 35th IEEE International Symposium on Computer Architecture and High Performance Computing, 2023
Enhancing Anonymity in NoC Communication to Counter Traffic Profiling by Hardware Trojans.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023
Understanding the Performance Impact of Queue-Based Resource Allocation in Scalable Disaggregated Memory Systems.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023
Modelling and Impact Analysis of Push Back Attack in 3D Bufferless Network on Chip.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023
PortBlocker: Detection and Mitigation of Hardware Trojan through Re-routing and Bypassing.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023
Exploring Trustable Paths in Network-on-Chip for Low-Slack Packets.
Proceedings of the 20th International SoC Design Conference, 2023
Wireless enabled Inter-Chiplet Communication in DNN Hardware Accelerators.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023
2022
FlitZip: Effective Packet Compression for NoC in MultiProcessor System-on-Chip.
IEEE Trans. Parallel Distributed Syst., 2022
Electronic, Wireless, and Photonic Network-on-Chip Security: Challenges and Countermeasures.
IEEE Des. Test, 2022
Revising NoC in Future Multicore-Based Consumer Electronics for Performance.
IEEE Consumer Electron. Mag., 2022
RIBiT: Reduced Intra-flit Bit Transitions for Bufferless NoC.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
ENDURA : Enhancing Durability of Multi Level Cell STT-RAM based Non Volatile Memory Last Level Caches.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
Hardware Trojan Mitigation for Securing On-chip Networks from Dead Flit Attacks.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
LOKI: A Hardware Trojan Affecting Multiple Components of an SoC.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Designing Data-Aware Network-on-Chip for Performance.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Design and Evaluation of a Rack-Scale Disaggregated Memory Architecture For Data Centers.
Proceedings of the 24th IEEE Int Conf on High Performance Computing & Communications; 8th Int Conf on Data Science & Systems; 20th Int Conf on Smart City; 8th Int Conf on Dependability in Sensor, 2022
DAReS: Deflection Aware Rerouting between Subnetworks in Bufferless On-Chip Networks.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
Securing On-chip Interconnect against Delay Trojan using Dynamic Adaptive Caging.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
2021
Data Criticality in Multithreaded Applications: An Insight for Many-Core Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2021
COPE: Reducing Cache Pollution and Network Contention by Inter-tile Coordinated Prefetching in NoC-based MPSoCs.
ACM Trans. Design Autom. Electr. Syst., 2021
Opportunistic Caching in NoC: Exploring Ways to Reduce Miss Penalty.
IEEE Trans. Computers, 2021
Traffic aware routing in 3D NoC using interleaved asymmetric edge routers.
Nano Commun. Networks, 2021
Data Criticality in Multi-Threaded Applications: An Insight for Many-Core Systems.
CoRR, 2021
Packet header attack by hardware trojan in NoC based TCMP and its impact analysis.
Proceedings of the NOCS '21: International Symposium on Networks-on-Chip, 2021
Dead flit attack on NoC by hardware trojan and its impact analysis.
Proceedings of the NoCArc '21: Proceedings of the 14th International Workshop on Network on Chip Architectures, Virtual Event, Greece, October 18, 2021
Improving Lifetime of Non-Volatile Memory Caches by Logical Partitioning.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
2020
Exploiting Data Resilience in Wireless Network-on-chip Architectures.
ACM J. Emerg. Technol. Comput. Syst., 2020
SECTAR: Secure NoC using Trojan Aware Routing.
Proceedings of the 14th IEEE/ACM International Symposium on Networks-on-Chip, 2020
Exploiting On-Chip Routers to Store Dirty Cache Blocks in Tiled Chip Multi-processors.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Improving Inference Latency and Energy of Network-on-Chip based Convolutional Neural Networks through Weights Compression.
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020
Reducing Off-Chip Miss Penalty by Exploiting Underutilised On-Chip Router Buffers.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020
Router Buffer Caching for Managing Shared Cache Blocks in Tiled Multi-Core Processors.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020
2019
Cost effective routing techniques in 2D mesh NoC using on-chip transmission lines.
J. Parallel Distributed Comput., 2019
ECAP: energy-efficient caching for prefetch blocks in tiled chip multiprocessors.
IET Comput. Digit. Tech., 2019
Performance Enhancement of Caches in TCMPs Using Near Vicinity Prefetcher.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
2L-2D Routing for Buffered Mesh Network-on-Chip.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019
DoLaR: Double Layer Routing for Bufferless Mesh Network-on-Chip.
Proceedings of the TENCON 2019, 2019
Analyzing networks-on-chip based deep neural networks.
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019
Asymmetric routing in 3D NoC using interleaved edge routers.
Proceedings of the 12th International Workshop on Network on Chip Architectures, 2019
Networks-on-Chip based Deep Neural Networks Accelerators for IoT Edge Devices.
Proceedings of the Sixth International Conference on Internet of Things: Systems, 2019
2018
Energy-efficient fault tolerant technique for deflection routers in two-dimensional mesh Network-on-Chips.
IET Comput. Digit. Tech., 2018
An Adaptive Deflection Router with Dual Injection and Ejection Units for Mesh NoCs.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
Traffic Aware Deflection Rerouting Mechanism for Mesh Network on Chip.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Source Hotspot Management in a Mesh Network on Chip.
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018
Implementation of a Novel Fault Tolerant Routing Technique for Mesh Network on Chip.
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018
Performance Enhancement of NoCs Using Single Cycle Deflection Routers and Adaptive Priority Schemes.
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018
Critical Packet Prioritisation by Slack-Aware Re-Routing in On-Chip Networks.
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018
Improving energy consumption of NoC based architectures through approximate communication.
Proceedings of the 7th Mediterranean Conference on Embedded Computing, 2018
ReDC: Reduced Deflection CHIPPER Router for Bufferless NoCs.
Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018
Approximate Wireless Networks-on-Chip.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018
2017
Impact of deflection history based priority on adaptive deflection router for mesh NoCs.
Electron. Gov. an Int. J., 2017
Implementation and analysis of hotspot mitigation in mesh NoCs by cost-effective deflection routing technique.
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017
Adaptive Packet Throttling Technique for Congestion Management in Mesh NoCs.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017
2015
Smart Port Allocation for Adaptive NoC Routers.
Proceedings of the 28th International Conference on VLSI Design, 2015
Dynamic migratory selection strategy for adaptive routing in mesh NoCs.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
2014
Implementation and Analysis of History-Based Output Channel Selection Strategies for Adaptive Routers in Mesh NoCs.
ACM Trans. Design Autom. Electr. Syst., 2014
An Energy Efficient Load Balancing Selection Strategy for Adaptive NoC Routers.
Proceedings of the 2014 International Workshop on Network on Chip Architectures, 2014
Study and analysis of various task scheduling algorithms in the cloud computing environment.
Proceedings of the 2014 International Conference on Advances in Computing, 2014
WeDBless: weighted deflection bufferless router for mesh NoCs.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
Minimally buffered single-cycle deflection router.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
SLIDER: Smart Late Injection DEflection Router for mesh NoCs.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013
DeBAR: deflection based adaptive router with minimal buffering.
Proceedings of the Design, Automation and Test in Europe, 2013
2012
TRACKER: A low overhead adaptive NoC router with load balancing selection strategy.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
2011
BOFAR: buffer occupancy factor based adaptive router for mesh NoCs.
Proceedings of the 4th International Workshop on Network on Chip Architectures, 2011