2024
A 0.88pJ/bit 112Gb/s PAM4 Transmitter with $1\mathrm{V}_{\text{ppd}}$ Output Swing and 5-Tap Analog FFE in 7nm FinFET CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration.
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Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2023
A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links.
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IEEE J. Solid State Circuits, 2023
Low power cryogenic RF ASICs for quantum computing.
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Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
A Cryo-CMOS Low-Power Semi-Autonomous Transmon Qubit State Controller in 14-nm FinFET Technology.
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IEEE J. Solid State Circuits, 2022
An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS.
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Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links.
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Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A Cryo-CMOS Low-Power Semi-Autonomous Qubit State Controller in 14nm FinFET Technology.
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Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A Cryo-CMOS Transmon Qubit Controller and Verification with FPGA Emulation.
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Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2020
Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14-nm SOI CMOS.
IEEE J. Solid State Circuits, 2020
Errata Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS".
IEEE J. Solid State Circuits, 2020
A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS.
IEEE J. Solid State Circuits, 2020
2019
A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14nm SOI CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2018
A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOS.
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IEEE J. Solid State Circuits, 2018
2016
A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration.
IEEE J. Solid State Circuits, 2016
2015
A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks.
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IEEE J. Solid State Circuits, 2015
The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.
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IEEE J. Solid State Circuits, 2015
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology.
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IEEE J. Solid State Circuits, 2015
A 25 Gb/s burst-mode receiver for low latency photonic switch networks.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015
A WDM-Compatible 4 × 32-Gb/s CMOS-driven electro-absorption modulator array.
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Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015
22.1 A 25Gb/s burst-mode receiver for rapidly reconfigurable optical networks.
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Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology.
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IEEE J. Solid State Circuits, 2014
5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8<sup>TM</sup> microprocessor.
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Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology.
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Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
Design techniques for CMOS backplane transceivers approaching 30-Gb/s data rates.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology.
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IEEE J. Solid State Circuits, 2012
An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects.
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IEEE J. Solid State Circuits, 2012
A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology.
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IEEE J. Solid State Circuits, 2012
Dual-Loop System of Distributed Microregulators With High DC Accuracy, Load Response Time Below 500 ps, and 85-mV Dropout Voltage.
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IEEE J. Solid State Circuits, 2012
A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS.
IEEE J. Solid State Circuits, 2012
Root cause identification of an hard-to-find on-chip power supply coupling fail.
Proceedings of the 2012 IEEE International Test Conference, 2012
A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology.
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Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2009
A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS.
IEEE J. Solid State Circuits, 2009
A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer With Current-Integrating Summers in 45-nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2009
Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2007
A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE.
IEEE J. Solid State Circuits, 2007
A 7Gb/s 9.3mW 2-Tap Current-Integrating DFE Receiver.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2006
A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology.
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IEEE J. Solid State Circuits, 2006
A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS.
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Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2003
A superconducting bandpass delta-sigma modulator for direct analog-to-digital conversion of microwave radio.
PhD thesis, 2003
2002
Superconducting bandpass ΔΣ modulator with 2.23-GHz center frequency and 42.6-GHz sampling rate.
IEEE J. Solid State Circuits, 2002
1992
A 155-MHz clock recovery delay- and phase-locked loop.
IEEE J. Solid State Circuits, December, 1992