AIM: Software and Hardware Co-design for Architecture-level IR-drop Mitigation in High-performance PIM.
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Proceedings of the 52nd Annual International Symposium on Computer Architecture, 2025
H<sup>2</sup>-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference.
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Proceedings of the 52nd Annual International Symposium on Computer Architecture, 2025
Theseus: Towards High-Efficiency Wafer-Scale Chip Design Space Exploration for Large Language Models.
CoRR, 2024
FD-CNN: A Frequency-Domain FPGA Acceleration Scheme for CNN-Based Image-Processing Applications.
ACM Trans. Embed. Comput. Syst., November, 2023
METRO: A Software-Hardware Co-Design of Interconnections for Spatial DNN Accelerators.
CoRR, 2021
Fork Path: Batching ORAM Requests to Remove Redundant Memory Accesses.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Development of Multi-video Based Virtual Classroom and Its Application in English as Second Language Learning.
Proceedings of the 2008 International Symposium on Computer Science and Computational Technology, 2008