Improving the throughput and delay performance of network processors by applying push model.
Proceedings of the 20th IEEE International Workshop on Quality of Service, 2012
Experience on Applying Push Model to Packet Processors in High Performance Routers.
Proceedings of the Global Communications Conference, 2010
Revisiting the Cache Effect on Multicore Multithreaded Network Processors.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
Conserving network processor power consumption by exploiting traffic variability.
ACM Trans. Archit. Code Optim., 2007
Program Mapping onto Network Processors by Recursive Bipartitioning and Refining.
Proceedings of the 44th Design Automation Conference, 2007
A low energy cache design for multimedia applications exploiting set access locality.
J. Syst. Archit., 2005
Enhancing Network Processor Simulation Speed with Statistical Input Sampling.
Proceedings of the High Performance Embedded Architectures and Compilers, 2005
Assertion-Based Design Exploration of DVS in Network Processor Architectures.
Proceedings of the 2005 Design, 2005
Low power network processor design using clock gating.
Proceedings of the 42nd Design Automation Conference, 2005
Assertion-based power/performance analysis of network processor architectures.
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004