Analysis of Conductance Variability in RRAM for Accurate Neuromorphic Computing.
Proceedings of the 25th IEEE Latin American Test Symposium, 2024
Optimization of digital transistors for low-cost and low-power IoT applications in 40nm technology.
Proceedings of the IEEE International Conference on Design, 2024
STATE: A Test Structure for Rapid Prediction of Resistive RAM Electrical Parameter Variability.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Simulation of state of the art EEPROM programming window closure during endurance degradation.
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021
Resistive RAM SET and RESET Switching Voltage Evaluation as an Entropy Source for Random Number Generation.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020
True random number generation exploiting SET voltage variability in resistive RAM memory arrays.
Proceedings of the 19th Non-Volatile Memory Technology Symposium, 2019
Light-Weight Cipher Based on Hybrid CMOS/STT-MRAM: Power/Area Analysis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Dual Detection of Heating and Photocurrent attacks (DDHP) Sensor using Hybrid CMOS/STT-MRAM.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
An Augmented OxRAM Synapse for Spiking Neural Network (SNN) Circuits.
Proceedings of the 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2019
Quantitative correlation between Flash and equivalent transistor for endurance electrical parameters extraction.
Microelectron. Reliab., 2018
Impact of a Laser Pulse on a STT-MRAM Bitcell: Security and Reliability Issues.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
MRAM: from STT to SOT, for security and memory.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018
Impact of resistive paths on NVM array reliability: Application to Flash & ReRAM memories.
Microelectron. Reliab., 2016
Impact of endurance degradation on the programming efficiency and the energy consumption of NOR flash memories.
Microelectron. Reliab., 2014
Access resistor modelling for EEPROM's retention test vehicle.
Microelectron. Reliab., 2013
Investigation of the effects of constant voltage stress on thin SiO<sub>2</sub> layers using dynamic measurement protocols.
Microelectron. Reliab., 2012
Effects of Lightly Doped Drain and Channel Doping Variations on Flash Memory Performances and Reliability.
J. Low Power Electron., 2012
Leakage paths identification in NVM using biased data retention.
Microelectron. Reliab., 2010
Modeling charge variation during data retention of MLC Flash memories.
Microelectron. Reliab., 2009
Extraction of 3D parasitic capacitances in 90 nm and 22 nm NAND flash memories.
Microelectron. Reliab., 2009