A Novel Design Technique for Enhanced Security and New Applications of Ferroelectric-Based Non-Volatile SRAM.

A Novel March Test Algorithm for Testing 8T SRAM-Based IMC Architectures.

Compute-In-Place Serial FeRAM: Enhancing Performance, Efficiency and Adaptability in Critical Embedded Systems.

Benefits of Design Assist Techniques on Performances and Reliability of a RRAM Macro.

An Optimal Open-Loop Strategy for Handling a Flexible Beam with a Robot Manipulator.

Intra-cell Resistive-Open Defect Analysis on a Foundry 8T SRAM-based IMC Architecture.

NimbleAI: Towards Neuromorphic Sensing-Processing 3D-integrated Chips.

Binary ReRAM-based BNN first-layer implementation.

An Automated Design Methodology for Computational SRAM Dedicated to Highly Data-Centric Applications: Invited Paper.

Low-Overhead Implementation of Binarized Neural Networks Employing Robust 2T2R Resistive RAM Bridges.

A Near-Instantaneous and Non-Invasive Erasure Design Technique to Protect Sensitive Data Stored in Secure SRAMs.

Storage Class Memory with Computing Row Buffer: A Design Space Exploration.

SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15, 000× Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency.

Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorization.

Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing.

Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture.

Prospects for energy-efficient edge computing with integrated HfO2-based ferroelectric devices.

Reliable ReRAM-based Logic Operations for Computing in Memory.

Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCubeTM Technology.

RRAM Crossbar Arrays for Storage Class Memory Applications: Throughput and Density Considerations.

Smart instruction codes for in-memory computing architectures compatible with standard SRAM interfaces.

Software platform dedicated for in-memory computing circuit evaluation.

Architecture, design and technology guidelines for crosspoint memories.

High density emerging resistive memories: What are the limits?

Design methodology for area and energy efficient OxRAM-based non-volatile flip-flop.

Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures.

DRC²: Dynamically Reconfigurable Computing Circuit based on memory architecture.

SneakPath compensation circuit for programming and read operations in RRAM-based CrossPoint architectures.

Low Standby Power Capacitively Coupled Sense Amplifier for wide voltage range operation of dual rail SRAMs.

27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking.

Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology.

Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology.

Optimization of a voltage sense amplifier operating in ultra wide voltage range with back bias design techniques in 28nm UTBB FD-SOI technology.

Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control.

Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs.

Can we go towards true 3-D architectures?

32nm and beyond Multi-VT Ultra-Thin Body and BOX FDSOI: From device to circuit.