2023
FrameD: framework for DNA-based data storage design, verification, and validation.
Bioinform., October, 2023
Reducing Read Amplification and Re-synthesis in DNA-based Archival Storage.
Proceedings of the IEEE International Conference on Rebooting Computing, 2023
Thoth: Bridging the Gap Between Persistently Secure Memories and Memory Interfaces of Emerging NVMs.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023
PreFlush: Lightweight Hardware Prediction Mechanism for Cache Line Flush and Writeback.
Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, 2023
2022
DINOS: Data INspired Oligo Synthesis for DNA Data Storage.
ACM J. Emerg. Technol. Comput. Syst., 2022
Horus: Persistent Security for Extended Persistence-Domain Memory Systems.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022
2021
Dolos: Improving the Performance of Persistent Applications in ADR-Supported Secure Memory.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
BBB: Simplifying Persistent Programming using Battery-Backed Buffers.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021
2020
Persistent Data Retention Models.
CoRR, 2020
The Case for Domain-Specialized Branch Predictors for Graph-Processing.
IEEE Comput. Archit. Lett., 2020
WET: Write Efficient Loop Tiling for Non-Volatile Main Memory.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
Efficient Checkpointing with Recompute Scheme for Non-volatile Main Memory.
ACM Trans. Archit. Code Optim., 2019
2018
Hardware Supported Permission Checks on Persistent Objects for Performance and Programmability.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018
Lazy Persistency: A High-Performing and Write-Efficient Software Persistency Technique.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018
2017
ReDirect: Reconfigurable Directories for Multicore Architectures.
ACM Trans. Archit. Code Optim., 2017
Leveraging near data processing for high-performance checkpoint/restart.
Proceedings of the International Conference for High Performance Computing, 2017
Hardware supported persistent object address translation.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017
Proteus: a flexible and fast software supported hardware logging approach for NVM.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017
Improving the effectiveness of searching for isomorphic chains in superword level parallelism.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017
Hiding the Long Latency of Persist Barriers Using Speculative Execution.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017
Characterizing the impact of soft errors across microarchitectural structures and implications for predictability.
Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017
Efficient Checkpointing of Loop-Based Codes for Non-volatile Main Memory.
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017
2016
An Accurate Cross-Layer Approach for Online Architectural Vulnerability Estimation.
ACM Trans. Archit. Code Optim., 2016
Lightweight runtime checking of C programs with RTC.
Comput. Lang. Syst. Struct., 2016
2015
Control-Flow Decoupling: An Approach for Timely, Non-Speculative Branching.
IEEE Trans. Computers, 2015
Runtime checking C programs.
Proceedings of the 30th Annual ACM Symposium on Applied Computing, 2015
Source Mark: A Source-Level Approach for Identifying Architecture and Optimization Agnostic Regions for Performance Analysis.
Proceedings of the 2015 IEEE International Symposium on Workload Characterization, 2015
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Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
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Proceedings of the 2015 International 3D Systems Integration Conference, 2015
2014
3D-enabled customizable embedded computer (3DECC).
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Proceedings of the 2014 International 3D Systems Integration Conference, 2014
2013
Automatic parallelization of fine-grained metafunctions on a chip multiprocessor.
ACM Trans. Archit. Code Optim., 2013
2012
Efficiently exploiting memory level parallelism on asymmetric coupled cores in the dark silicon era.
ACM Trans. Archit. Code Optim., 2012
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012
HiRe: using hint & release to improve synchronization of speculative threads.
Proceedings of the International Conference on Supercomputing, 2012
Efficient and accurate data dependence profiling using software signatures.
Proceedings of the 10th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2012
2011
HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011
Automatic parallelization of fine-grained meta-functions on a chip multiprocessor.
Proceedings of the CGO 2011, 2011
2010
MMT: Exploiting fine-grained parallelism in dynamic memory management.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010
Speculative parallelization of partial reduction variables.
Proceedings of the CGO 2010, 2010
2009
SoftSig: Software-Exposed Hardware Signatures for Code Analysis and Optimization.
IEEE Micro, 2009
The Bulk Multicore architecture for improved programmability.
Commun. ACM, 2009
Memory management thread for heap allocation intensive sequential applications.
Proceedings of the 10th workshop on MEmory performance, 2009
2007
Efficient Support for Speculative Tasking
PhD thesis, 2007
BulkSC: bulk enforcement of sequential consistency.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007
CAP: Criticality analysis for power-efficient speculative multithreading.
Proceedings of the 25th International Conference on Computer Design, 2007
2006
CAVA: Using checkpoint-assisted value prediction to hide L2 misses.
ACM Trans. Archit. Code Optim., 2006
Energy-Efficient Thread-Level Speculation.
IEEE Micro, 2006
POSH: a TLS compiler that exploits program structure.
Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2006
Scalable Cache Miss Handling for High Memory-Level Parallelism.
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006
Bulk Disambiguation of Speculative Threads in Multiprocessors.
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006
2005
Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilation.
Proceedings of the 19th Annual International Conference on Supercomputing, 2005
Thread-Level Speculation on a CMP can be energy efficient.
Proceedings of the 19th Annual International Conference on Supercomputing, 2005
2004
CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction.
IEEE Comput. Archit. Lett., 2004
2001
Handling crosscutting constraints in domain-specific modeling.
Commun. ACM, 2001