×
2012
A 576 Mb DRAM with 16-channel 10.3125Gbps serial I/O and 14.5 ns latency.
[DOI]
Socrates D. Vamvakos
,
Bendik Kleveland
,
Dipak K. Sikdar
,
B. K. Ahuja
,
Haidang Lin
,
Jayaprakash Balachandran
,
Wignes Balakrishnan
,
Aldo Bottelli
,
Jawji Chen
,
Xiaole Chen
,
Jae Choi
,
Jeong Choi
,
Rajesh Chopra
,
Sanjay Dabral
,
Kalyan Dasari
,
Ronald B. David
,
Shaishav Desai
,
Claude R. Gauthier
,
Mahmudul Hassan
,
Kuo-Chiang Hsieh
,
Ramosan Canagasaby
,
Jeff Kumala
,
E. P. Kwon
,
Ben Lee
,
Ming Liu
,
Gurupada Mandal
,
Sundari Mitra
,
Byeong Cheol Na
,
Siddharth Panwar
,
Jay Patel
,
Chethan Rao
,
Vithal Rao
,
Richard Rouse
,
Ritesh Saraf
,
Subramanian Seshadri
,
Jae-K. Sim
,
Clement Szeto
,
Alvin Wang
,
Jason Yeung
Proceedings of the 38th European Solid-State Circuit conference, 2012