Interconnect Architecture Design for Emerging Integration Technologies
PhD thesis, 2020
Network-on-Chip Design Guidelines for Monolithic 3-D Integration.
IEEE Micro, 2019
Investigation of Cost-Optimal Network-on-Chip for Passive and Active Interposer Systems.
Proceedings of the 21st ACM/IEEE International Workshop on System Level Interconnect Prediction, 2019
Alleviating Irregularity in Graph Analytics Acceleration: a Hardware/Software Co-Design Approach.
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Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019
Balancing Memory Accesses for Energy-Efficient Graph Analytics Accelerators.
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Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
Near-Data Acceleration of Privacy-Preserving Biomarker Search with 3D-Stacked Memory.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Efficient System Architecture in the Era of Monolithic 3D: Dynamic Inter-tier Interconnect and Processing-in-Memory.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
There and Back Again: Optimizing the Interconnect in Networks of Memory Cubes.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017
A unified memory network architecture for in-memory computing in commodity servers.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016
Cost and Thermal Analysis of High-Performance 2.5D and 3D Integrated Circuit Design Space.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Scalable memory fabric for silicon interposer-based multi-core systems.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
Cost analysis and cost-driven IP reuse methodology for SoC design based on 2.5D/3D integration.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016