Multi-Mode Borderguard Controllers for Efficient On-Chip Communication in Heterogeneous Digital/Analog Neural Processing Units.

Analog-AI Hardware Accelerators for Low-Latency Transformer-Based Language Models (Invited).

A Precision-Optimized Fixed-Point Near-Memory Digital Processing Unit for Analog In-Memory Computing.

Architectures and Circuits for Analog-memory-based Hardware Accelerators for Deep Neural Networks (Invited).

Impact of Phase-Change Memory Drift on Energy Efficiency and Accuracy of Analog Compute-in-Memory Deep Learning Inference (Invited).

AnalogNAS: A Neural Network Design Framework for Accurate Inference with Analog In-Memory Computing.

End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture.

Scale up your In-Memory Accelerator: Leveraging Wireless-on-Chip Communication for AIMC-based CNN Inference.

Accurate Weight Mapping in a Multi-Memristive Synaptic Unit.

Mushroom-Type phase change memory with projection liner: An array-level demonstration of conductance drift and noise mitigation.

Architecting more than Moore: wireless plasticity for massive heterogeneous computer architectures (WiPLASH).

End-to-end 100-TOPS/W Inference With Analog In-Memory Computing: Are We There Yet?

Accurate Emulation of Memristive Crossbar Arrays for In-Memory Computing.

ESSOP: Efficient and Scalable Stochastic Outer Product Architecture for Deep Learning.

Computational memory-based inference and training of deep neural networks.

Multi-ReRAM Synapses for Artificial Neural Network Training.

Phase-Change Memory Models for Deep Learning Training and Inference.

Impact of conductance drift on multi-PCM synaptic architectures.

Mixed-precision architecture based on computational memory for training deep neural networks.

An efficient synaptic architecture for artificial neural networks.

Fatiguing STDP: Learning from spike-timing codes in the presence of rate codes.

Improved Deep Neural Network Hardware-Accelerators Based on Non-Volatile-Memory: The Local Gains Technique.

Large-scale neural networks implemented with Non-Volatile Memory as the synaptic weight element: Impact of conductance response.

Non-volatile memory as hardware synapse in neuromorphic computing: A first look at reliability issues.

A hardware-oriented dynamically adaptive disparity estimation algorithm and its real-time hardware.