A Highly Digital 143.2-dB DR Sub-1° Phase Error Impedance Monitoring IC With Pulsewidth Modulation Frontend.
IEEE J. Solid State Circuits, April, 2024
A Highly-Digital PWM-Based Impedance Monitoring IC with 143.2dB DR and 17.7fFrms Resolution.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A 0.02mm<sup>2</sup> 100dB-DR Impedance Monitoring IC with PWM-Dual GRO Architecture.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019