A Processing-using-Memory Architecture for Commodity DRAM Devices with Enhanced Compatibility and Reliability.
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024
Effective zero compression on ReRAM-based sparse DNN accelerators.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
A Specialized Architecture for Object Serialization with Applications to Big Data Analytics.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020
Sybil Tolerant Consensus Method Using Mutual Proof of Validation.
Proceedings of the IECC 2020: 2nd International Electronics Communication Conference, 2020
Unlocking Wordline-level Parallelism for Fast Inference on RRAM-based DNN Accelerator.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Detecting Arrivals and Departure of Subway Train Using Linear Accelerometer.
Proceedings of the 17th Annual International Conference on Mobile Systems, 2019
A 12-Gb/s Stacked Dual-Channel Interface for CMOS Image Sensor Systems.
Sensors, 2018
A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process.
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Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Subway Stop/Departure Detection using a Magnetic Sensor of the Smartphone.
Proceedings of the 2nd International Conference on Vision, Image and Signal Processing, 2018
A 12-Gb/s dual-channel transceiver for CMOS image sensor systems.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
New detection method and countermeasure of cyber attacks in mix networks.
Multim. Tools Appl., 2015