Digital background calibration algorithm for pipelined ADC based on time-delay neural network with genetic algorithm feature selection.
Integr., 2025
Genetic neural network based background calibration method for pipeline ADC.
Microelectron. J., 2024
Fully Digital Calibration Technique for Channel Mismatch of TIADC at Any Frequency.
IEICE Trans. Electron., March, 2023
All-digital calibration algorithm based on channel multiplexing for TI-ADCs.
Microelectron. J., 2022
A fully digital mismatch calibration algorithm for Time-Interleaved ADCs.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
A split-based fully digital feedforward background calibration technique for timing mismatch in TIADC.
Integr., 2020
Calibration of timing mismatch in TIADC based on monotonicity detecting of sampled data.
IEICE Electron. Express, 2020
A channel multiplexing digital calibration technique for timing mismatch of time-interleaved ADCs.
IEICE Electron. Express, 2019
A 0.6V 19.5μW 80dB DR ΔΣ Modulator with SA-Quantizers and Digital Feedforward Path.
J. Circuits Syst. Comput., 2017
All-digital background calibration technique for timing mismatch of time-interleaved ADCs.
Integr., 2017
A Low Complexity All-Digital Background Calibration Technique for Time-Interleaved ADCs.
VLSI Design, 2016
An efficient digital calibration technique for timing mismatch in time-interleaved ADCs.
IEICE Electron. Express, 2016