Pulsed-Latch Utilization for Clock-Tree Power Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Load-balanced clock tree synthesis with adjustable delay buffer insertion for clock skew reduction in multiple dynamic supply voltage designs.
ACM Trans. Design Autom. Electr. Syst., 2012
Pulsed-latch-based clock tree migration for dynamic power reduction.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
An efficient algorithm of adjustable delay buffer insertion for clock skew minimization in multiple dynamic supply voltage designs.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011