A Multiply-Less Approximate SRAM Compute-In-Memory Macro for Neural-Network Inference.
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IEEE J. Solid State Circuits, February, 2025
A 266F<sup>2</sup> Ultra Stable Differential NOR-Structured Physically Unclonable Function With < 6x10<sup>-9</sup> Bit Error Rate Through Efficient Redundancy Strategy.
IEEE Trans. Circuits Syst. II Express Briefs, December, 2024
Contrastive Incomplete Cross-Modal Hashing.
IEEE Trans. Knowl. Data Eng., November, 2024
CASCADE: A Framework for CNN Accelerator Synthesis With Concatenation and Refreshing Dataflow.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2024
A 28nm 8Kb Reconfigurable SRAM Computing-In-Memory Macro With Input-Sparsity Optimized DTC for Multi-Mode MAC Operations.
IEEE Trans. Circuits Syst. II Express Briefs, July, 2024
A 4-bit Calibration-Free Computing-In-Memory Macro With 3T1C Current-Programed Dynamic-Cascode Multi-Level-Cell eDRAM.
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IEEE J. Solid State Circuits, March, 2024
SeqAfford: Sequential 3D Affordance Reasoning via Multimodal Large Language Model.
CoRR, 2024
Exploiting Descriptive Completeness Prior for Cross Modal Hashing with Incomplete Labels.
Proceedings of the Advances in Neural Information Processing Systems 38: Annual Conference on Neural Information Processing Systems 2024, 2024
30.5 A Variation-Tolerant In-eDRAM Continuous-Time Ising Machine Featuring 15-Level Coefficients and Leaked Negative-Feedback Annealing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
A 181.8dB FoMs Zoom Capacitance-to-Digital Converter with kT/C Noise Cancellation and Dead Band Operation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
A 28nm 128TFLOPS/W Computing-In-Memory Engine Supporting One-Shot Floating-Point NN Inference and On-Device Fine-Tuning for Edge AI.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
A 28nm 32Kb SRAM Computing-in-Memory Macro With Hierarchical Capacity Attenuator and Input Sparsity-Optimized ADC for 4b Mac Operation.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023
Modality-Invariant Asymmetric Networks for Cross-Modal Hashing.
IEEE Trans. Knowl. Data Eng., May, 2023
SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
A Calibration-Free 15-level/Cell eDRAM Computing-in-Memory Macro with 3T1C Current-Programmed Dynamic-Cascoded MLC achieving 233-to-304-TOPS/W 4b MAC.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A 9.7fJ/Conv.-Step Capacitive Sensor Readout Circuit with Incremental Zoomed Time Domain Quantization.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A 65 nm 73 kb SRAM-Based Computing-In-Memory Macro With Dynamic-Sparsity Controlling.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Cognitive multi-modal consistent hashing with flexible semantic transformation.
Inf. Process. Manag., 2022