Characterization and Exploration of Latch Checkers for Efficient RAS Protection.
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023
Energy Efficiency Boost in the AI-Infused POWER10 Processor.
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Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
SERMiner : A Framework for Early-stage Reliability Estimation for IBM Processors.
Proceedings of the 51st Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2021
Generation of Stressmarks for Early Stage Soft-Error Modeling.
Proceedings of the 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2019
Very Low Voltage (VLV) Design.
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Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Quantifying sources of error in McPAT and potential impacts on architectural studies.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015
Empirically derived abstractions in uncore power modeling for a server-class processor chip.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Design for low power and power management in IBM Blue Gene/Q.
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IBM J. Res. Dev., 2013
Application-level power and performance characterization and optimization on IBM Blue Gene/Q systems.
IBM J. Res. Dev., 2013
Power management of multi-core chips: Challenges and pitfalls.
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Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Abstraction and microarchitecture scaling in early-stage power modeling.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011
Power-efficient, reliable microprocessor architectures: modeling and design methods.
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Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors.
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Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005
Interlocked Synchronous Pipelines.
PhD thesis, 2004
Improved clock-gating through transparent pipelining.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004
Microarchitectural techniques for power gating of execution units.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004
Efficient algorithms for exact two-level hazard-free logic minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
Early-Stage Definition of LPX: A Low Power Issue-Execute Processor.
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Proceedings of the Power-Aware Computer Systems, Second International Workshop, 2002
Synchronous Interlocked Pipelines.
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002
Efficient Exact Two-Level Hazard-Free Logic Minimization.
Proceedings of the 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 2001
Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors.
IEEE Micro, 2000
Achieving Fast and Exact Hazard-Free Logic Minimization of Extended Burst-Mode gC Finite State Machines.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
High-Level Asynchronous System Design Using the ACK Framework.
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000
Corrections To application-specific Programmable Control For High-performance Asynchronous Circuits.
Proc. IEEE, 1999
Application-specific programmable control for high-performance asynchronous circuits.
Proc. IEEE, 1999
Asynchronous Microengines for Efficient High-level Control.
Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97), 1997
Synthesis for Hazard-free Customized CMOS Complex-Gate Networks Under Multiple-Input Changes.
Proceedings of the 33st Conference on Design Automation, 1996
A Technique for Synthesizing Distributed Burst-mode Circuits.
Proceedings of the 33st Conference on Design Automation, 1996