SEFsim: A Statistically-Guided Fast DRAM Simulator.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2024
Observed Memory Bandwidth and Power Usage on FPGA Platforms with OneAPI and Vitis HLS: A Comparison with GPUs.
Proceedings of the High Performance Computing, 2023
ERAS: A Flexible and Scalable Framework for Seamless Integration of RTL Models with Structural Simulation Toolkit.
Proceedings of the IEEE International Symposium on Workload Characterization, 2023
MultiGrid on FPGA Using Data Parallel C++.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022
Towards a scatter-gather architecture: hardware and software issues.
Proceedings of the International Symposium on Memory Systems, 2019
Analyzing allocation behavior for multi-level memory.
Proceedings of the Second International Symposium on Memory Systems, 2016
Multi-Level Memory Policies: What You Add Is More Important Than What You Take Out.
Proceedings of the Second International Symposium on Memory Systems, 2016
The Potential and Perils of Multi-Level Memory.
Proceedings of the 2015 International Symposium on Memory Systems, 2015
Fractal++: Closing the performance gap between fractal and conventional coherence.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014
High-performance fractal coherence.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2014
Wait-n-GoTM: improving HTM performance by serializing cyclic dependencies.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2013
EffiCuts: optimizing packet classification for memory and throughput.
Proceedings of the ACM SIGCOMM 2010 Conference on Applications, 2010
Timetraveler: exploiting acyclic races for optimizing memory race recording.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010