Pushing the Boundaries of AI Chips: From Monolithic 3D CMOS to Cryogenic Computing.
Proceedings of the Design, Automation & Test in Europe Conference, 2025
Technology Mapping for Cryogenic CMOS Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
Impact of Self-Heating in 5nm FinFETs at Cryogenic Temperatures for Reliable Quantum Computing: Device-Circuit Interaction.
Proceedings of the IEEE International Reliability Physics Symposium, 2024
FerroX: A GPU-accelerated, 3D phase-field simulation framework for modeling ferroelectric devices.
Comput. Phys. Commun., September, 2023
Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023
Robust Compact Model of High-Voltage MOSFET's Drift Region.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs.
IEEE Open J. Circuits Syst., 2023
5nm FinFET Cryogenic SRAM Evaluation for Quantum Computing.
Proceedings of the Device Research Conference, 2023
Design Automation for Cryogenic CMOS Circuits.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Compact Model for Trap Assisted Tunneling based GIDL.
Proceedings of the Device Research Conference, 2022
On the Resiliency of NCFET Circuits Against Voltage Over-Scaling.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Impact of Variability on Processor Performance in Negative Capacitance FinFET Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
Impact of Radiation on Negative Capacitance FinFET.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
NCFET to Rescue Technology Scaling: Opportunities and Challenges.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
NCFET-Aware Voltage Scaling.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
Performance, Power and Cooling Trade-Offs with NCFET-based Many-Cores.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Negative Capacitance Transistor to Address the Fundamental Limitations in Technology Scaling: Processor Performance.
IEEE Access, 2018
Designing energy efficient and hysteresis free negative capacitance FinFET with negative DIBL and 3.5X ION using compact modeling approach.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016