Reliability and Variability-Aware DTCO Flow: Demonstration of Projections to N3 FinFET and Nanosheet Technologies.

1.5-nm Node Surrounding Gate Transistor (SGT)-SRAM Cell with Staggered Pillar and Self-Aligned Process for Gate, Bottom Contact, and Pillar.

Cell Designer - a Comprehensive TCAD-Based Framework for DTCO of Standard Logic Cells.