Understanding and Modeling Opposite Impacts of Self-Heating on Hot-Carrier Degradation in n- and p-Channel Transistors.
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Proceedings of the IEEE International Reliability Physics Symposium, 2022
Significant Enhancement of HCD and TDDB in CMOS FETs by Mechanical Stress.
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Proceedings of the IEEE International Reliability Physics Symposium, 2022
Innovations in Transistor Architecture and Device Connectivity for Advanced Logic Scaling.
Proceedings of the International Conference on IC Design and Technology, 2022
Scalability comparison between raised- and embedded-SiGe source/drain structures for Si<sub>0.55</sub>Ge<sub>0.45</sub> implant free quantum well pFET.
Microelectron. Reliab., 2018
PPAC scaling enablement for 5nm mobile SoC technology.
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Proceedings of the 47th European Solid-State Device Research Conference, 2017
Beyond-Si materials and devices for more Moore and more than Moore applications.
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Proceedings of the International Conference on IC Design and Technology, 2016
Lateral NWFET optimization for beyond 7nm nodes.
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Proceedings of the 2015 International Conference on IC Design & Technology, 2015
Assessment of SiGe quantum well transistors for DRAM peripheral applications.
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Proceedings of the 2015 International Conference on IC Design & Technology, 2015
FinFET stressor efficiency on alternative wafer and channel orientations for the 14 nm node and below.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps.
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Proceedings of the IEEE International Conference on IC Design & Technology, 2012
Superior reliability and reduced Time-Dependent variability in high-mobility SiGe channel pMOSFETs for VLSI logic applications.
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Proceedings of the IEEE International Conference on IC Design & Technology, 2012
An analytical compact model for estimation of stress in multiple Through-Silicon Via configurations.
Proceedings of the Design, Automation and Test in Europe, 2011
Analysis of microbump induced stress effects in 3D stacked IC technologies.
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Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011