Complex IF Harmonic Rejection Mixer for Non-Contiguous Dual Carrier Reception in 65 nm CMOS.
IEEE J. Solid State Circuits, 2013
A receiver for LTE Rel-11 and beyond supporting non-contiguous carrier aggregation.
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Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Simultaneous Reception and Scanning Using Complex IF Radio Architectures.
Proceedings of the 74th IEEE Vehicular Technology Conference, 2011
Pulsewidth control loop in high-speed CMOS clock buffers.
IEEE J. Solid State Circuits, 2000
A layout-based schematic method for very high-speed CMOS cell design.
IEEE Trans. Very Large Scale Integr. Syst., 1999
Vector Transfer by Self-Tested Self-Synchronization for Parallel Systems.
IEEE Trans. Parallel Distributed Syst., 1999
Methodology of layout based schematic and its usage in efficient high performance CMOS design.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
High speed multistage CMOS clock buffers with pulse width control loop.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
High speed interface for system-on-chip design by self-tested self-synchronization.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Self-Synchronized Vector Transfer for High Speed Parallel Systems.
Proceedings of the International Conference on Parallel and Distributed Systems, 1998
Efficient High-Speed CMOS Design by Layout Based Schematic Method.
Proceedings of the 24th EUROMICRO '98 Conference, 1998
Automatic extraction of human facial features.
Signal Process. Image Commun., 1996