SEChecker: A Sequential Equivalence Checking Framework Based on Kth Invariants.
IEEE Trans. Very Large Scale Integr. Syst., 2009
Multiple-Fault Diagnosis Based On Adaptive Diagnostic Test Pattern Generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Pseudofunctional testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
IChecker: An Efficient Checker for Inductive Invariants.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006
Pseudo-Functional Scan-based BIST for Delay Fault.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005
Accurate Diagnosis of Multiple Faults.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Sequential equivalence checking based on k-th invariants and circuit SAT solving.
Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005
An Efficient Sequential SAT Solver With Improved Search Strategies.
Proceedings of the 2005 Design, 2005
Constraint extraction for pseudo-functional scan-based delay testing.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
A Signal Correlation Guided Circuit-SAT Solver.
J. Univers. Comput. Sci., 2004
A Circuit SAT Solver With Signal Correlation Guided Learning.
Proceedings of the 2003 Design, 2003
A signal correlation guided ATPG solver and its applications for solving difficult industrial cases.
Proceedings of the 40th Design Automation Conference, 2003