FDM: Fused Double-Multiply Design for Low-Latency and Area- and Power-Efficient Implementation.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024
An Optimized Architecture for Computing the Square Root of Complex Numbers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
High-Throughput Low-Latency Pipelined Divider for Single-Precision Floating-Point Numbers.
IEEE Trans. Very Large Scale Integr. Syst., 2022
ML-PLAC: Multiplierless Piecewise Linear Approximation for Nonlinear Function Evaluation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A New Design of a CMOS Vertical Hall Sensor with a Low Offset.
Sensors, 2022
An optimized hardware implementation of the CORDIC algorithm.
IEICE Electron. Express, 2022
Reconfigurable Multifunction Computing Unit Using an Universal Piecewise Linear Method.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
PWL-Based Architecture for the Logarithmic Computation of Floating-Point Numbers.
IEEE Trans. Very Large Scale Integr. Syst., 2021
Ultralow-Latency VLSI Architecture Based on a Linear Approximation Method for Computing Nth Roots of Floating-Point Numbers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A New Design of a Single-Device 3D Hall Sensor: Cross-Shaped 3D Hall Sensor.
Sensors, 2018
Influences of an Aluminum Covering Layer on the Performance of Cross-Like Hall Devices.
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Sensors, 2016
Performance Comparison of Cross-Like Hall Plates with Different Covering Layers.
Sensors, 2015
A more accurate circuit model for CMOS Hall cross with non-linear resistors and JFETs.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014