2024
Neural Dynamics Model of Visual Decision-Making: Learning from Human Experts.
CoRR, 2024
A Semantic Verifier for Optimizing Small-Scale Large Language Models on Reasoning Tasks.
Proceedings of the IEEE International Conference on Systems, Man, and Cybernetics, 2024
Reasoning Knowledge Transfer for Logical Table-to-Text Generation.
Proceedings of the International Joint Conference on Neural Networks, 2024
2021
BrainQuake: An Open-Source Python Toolbox for the Stereoelectroencephalography Spatiotemporal Analysis.
Frontiers Neuroinformatics, 2021
2020
Joint Partial Optimal Transport for Open Set Domain Adaptation.
Proceedings of the Twenty-Ninth International Joint Conference on Artificial Intelligence, 2020
Positive Contrast Susceptibility MR Imaging Using GPU-based Primal-Dual Algorithm.
Proceedings of the 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2020
2014
Efficient Check Node Processing Architectures for Non-binary LDPC Decoding Using Power Representation.
J. Signal Process. Syst., 2014
Finite Alphabet Iterative Decoders for LDPC Codes: Optimization, Architecture and Analysis.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
2013
Relaxed Min-Max Decoder Architectures for Nonbinary Low-Density Parity-Check Codes.
IEEE Trans. Very Large Scale Integr. Syst., 2013
Low-energy and low-latency error-correction for phase change memory.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Low-complexity finite alphabet iterative decoders for LDPC codes.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Facial Expression Recognition Based on Gabor Wavelet Phase Features.
Proceedings of the Seventh International Conference on Image and Graphics, 2013
The Knowledge Service Project in the Era of Big Data.
Proceedings of the IEEE International Congress on Big Data, 2013
2012
Low-Complexity Reliability-Based Message-Passing Decoder Architectures for Non-Binary LDPC Codes.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Low-power LDPC decoding based on iteration prediction.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
Reduced-Complexity Decoder Architecture for Non-Binary LDPC Codes.
IEEE Trans. Very Large Scale Integr. Syst., 2011
Efficient Partial-Parallel Decoder Architecture for Quasi-Cyclic Nonbinary LDPC Codes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
Reliability-Driven ECC Allocation for Multiple Bit Error Resilience in Processor Cache.
IEEE Trans. Computers, 2011
Low-complexity architectures for reliability-based message-passing non-binary LDPC decoding.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
An efficient architecture for iterative soft reliability-based majority-logic non-binary LDPC decoding.
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011
2010
Partial-parallel decoder architecture for quasi-cyclic non-binary LDPC codes.
Proceedings of the IEEE International Conference on Acoustics, 2010
Reduced-latency scheduling scheme for min-max non-binary LDPC decoding.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010