IEEE Des. Test Comput., 2010
Empirical Validation of Yield Recovery Using Idle-Cycle Insertion.
IEEE Des. Test Comput., 2007
Response compaction with any number of unknowns using a new LFSR architecture.
Proceedings of the 42nd Design Automation Conference, 2005
Delay Defect Screening using Process Monitor Structures.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004
ELF-Murphy Data on Defects and Test Sets.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004
Speed Clustering of Integrated Circuits.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
Modern Test Techniques: Tradeoffs, Synergies, and Scalable Benefits.
J. Electron. Test., 2003
Efficient Seed Utilization for Reseeding based Compression.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003
ATPG Padding And ATE Vector Repeat Per Port For Reducing Test Data Volume.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Test Economics for Multi-site Test with Modern Cost Reduction Techniques.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002
Test Vector Compression Using EDA-ATE Synergies.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002
Packet-Based Input Test Data Compression Techniques.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
Tackling test trade-offs from design, manufacturing to market using economic modeling.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001