2015
Fast eye diagram analysis for high-speed CMOS circuits.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2013
Efficient moment estimation with extremely small sample size via bayesian inference for analog/mixed-signal validation.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
Power grid effects and their impact on-die.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
2010
Verification and Codesign of the Package and Die Power Delivery System Using Wavelets.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Power delivery dynamics and its impact on silicon validation.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Path coverage based functional test generation for processor marginality validation.
Proceedings of the 2011 IEEE International Test Conference, 2010
On-die power grids: the missing link.
Proceedings of the 47th Design Automation Conference, 2010
2009
A microarchitecture-based framework for pre- and post-silicon power delivery analysis.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009
2008
Speedpath prediction based on learning from a small set of examples.
Proceedings of the 45th Design Automation Conference, 2008
2007
Power Grid Physics and Implications for CAD.
IEEE Des. Test Comput., 2007
A nonlinear cell macromodel for digital applications.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Silicon Speedpath Measurement and Feedback into EDA flows.
Proceedings of the 44th Design Automation Conference, 2007
2006
Power grid physics and implications for CAD.
Proceedings of the 43rd Design Automation Conference, 2006
A multi-port current source model for multiple-input switching effects in CMOS library cells.
Proceedings of the 43rd Design Automation Conference, 2006
2004
Fast flip-chip power grid analysis via locality and grid shells.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
2003
Early electrical wire projections and implications.
Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003
2001
Experience with building a commodity Intel-based ccNUMA system.
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IBM J. Res. Dev., 2001
1999
SRC physical design top ten problem.
Proceedings of the 1999 International Symposium on Physical Design, 1999
1998
Interconnect and substrate modeling and analysis: an overview.
IEEE J. Solid State Circuits, 1998
1997
Physical design challenges for performance.
Proceedings of the 1997 International Symposium on Physical Design, 1997
1996
Efficient Full-Wave Electromagnetic Analysis via Model-Order Reduction of Fast Integral Transforms.
Proceedings of the 33st Conference on Design Automation, 1996
1995
Analysis of interconnect networks using complex frequency hopping (CFH).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995
1993
Simulating 3-D retarded interconnect models using complex frequency hopping (CFH).
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993
Addressing High-Speed Interconnect Issues in Asymptotic Waveform Evaluation.
Proceedings of the 30th Design Automation Conference. Dallas, 1993
1992
Generalized Moment-Matching Methods for Transient Analysis of Interconnect Networks.
Proceedings of the 29th Design Automation Conference, 1992
1988
Parallel PLA fault simulation based on Boolean vector operations.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988