Automatic Retiming of Two-Phase Latch-Based Resilient Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Adding Conditionality to Resilient Bundled-Data Designs.
Proceedings of the 22nd IEEE International Symposium on Asynchronous Circuits and Systems, 2016
TDTB error detecting latches: Timing violation sensitivity analysis and optimization.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Blade - A Timing Violation Resilient Asynchronous Template.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015
Performance Optimization and Analysis of Blade Designs under Delay Variability.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015
Performance and Area Optimization of a Bundled-Data Intel Processor through Resynthesis.
Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014
A non-uniform sampling ADC architecture with embedded alias-free asynchronous filter.
Proceedings of the 2012 IEEE Global Communications Conference, 2012