2024
An Energy-Efficient Differential Frame Convolutional Accelerator with on-Chip Fusion Storage Architecture and Pixel-Level Pipeline Data Flow.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
An Efficient Spiking Convolutional Architecture with Compressed Address Event Representation and Adaptive Delay Asynchronous Clocks.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2024
2023
A multichannel readout integrated circuit with column-wise pseudo differential extended counting ADCs for an uncooled infrared focal plane array based on silicon diodes.
Microelectron. J., September, 2023
Multimodal Affective States Recognition Based on Multiscale CNNs and Biologically Inspired Decision Fusion Model.
IEEE Trans. Affect. Comput., 2023
2022
ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator.
IEEE Trans. Very Large Scale Integr. Syst., 2022
An Event-driven Spiking Neural Network Accelerator with On-chip Sparse Weight.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
A 64K-Neuron 64M-1b-Synapse 2.64pJ/SOP Neuromorphic Chip With All Memory on Chip for Spike-Based Models in 65nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A 28-nm 0.34-pJ/SOP Spike-Based Neuromorphic Processor for Efficient Artificial Neural Network Implementations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Low Power Readout Integrated Circuit with PFM-based ADCs Employing Residue Quantization for Uncooled Infrared Imagers.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
A Novel Circuit Authentication Scheme Based on Partial Polymorphic Gates.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2021
2020
Fully on-chip clock jitter and skew measurement scheme via incoherent subsampling.
Microelectron. J., 2020
A 3D Convolutional Neural Network for Emotion Recognition based on EEG Signals.
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020
2019
A New Method for Futures Price Trends Forecasting Based on BPNN and Structuring Data.
IEICE Trans. Inf. Syst., 2019
Multimodal Emotion Recognition Model using Physiological Signals.
CoRR, 2019
FPGA Implementation of Quantized Convolutional Neural Networks.
Proceedings of the 19th IEEE International Conference on Communication Technology, 2019
Perceptual Fast CU Size Decision Algorithm for AVS2 Intra Coding.
Proceedings of the Fifth IEEE International Conference on Multimedia Big Data, 2019
Designing a 3D Graphics Processor for Mobile Applications.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Improved Discrete Wavelet Analysis and Principal Component Analysis for EEG Signal Processing.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
Evaluation of Dynamic-Adjusting Threshold-Voltage Scheme for Low-Power FinFET Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2018
Design of Low-Power High-Performance FinFET Standard Cells.
Circuits Syst. Signal Process., 2018
A 108fs<sub>rms</sub> 0.45mW 100MS/s 1.25MHz bandwidth multi-bit ΔΣ time-to-digital converter with dynamic element matching.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A Novel Polymorphic Gate Based Circuit Fingerprinting Technique.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Polymorphic gate based IC watermarking techniques.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
High-Performance Noninvasive Side-Channel Attack Resistant ECC Coprocessor for GF(2m ).
IEEE Trans. Ind. Electron., 2017
Improving DFA attacks on AES with unknown and random faults.
Sci. China Inf. Sci., 2017
A practical cold boot attack on RSA private keys.
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017
2016
Low Power High Performance FinFET Standard Cells Based on Mixed Back Biasing Technology.
IEICE Trans. Electron., 2016
Efficient Weak Signals Acquisition Strategy for GNSS Receivers.
IEICE Trans. Commun., 2016
Ultralow-power high-speed flip-flop based on multimode FinFETs.
Sci. China Inf. Sci., 2016
Improving tracking accuracy with subcarrier assistance and code monitoring for BOC modulated signal.
Comput. Electr. Eng., 2016
2015
Balance Differential Coherent Bit Synchronization Algorithm for GNSS Receiver.
IEICE Trans. Commun., 2015
Key characterization factors of accurate power modeling for FinFET circuits.
Sci. China Inf. Sci., 2015
Employing the mixed FBB/RBB in the design of FinFET logic gates.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
A high-efficient and accurate fault model aiming at FPGA-based AES cryptographic applications.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2014
Effective PPS Signal Generation with Predictive Synchronous Loop for GPS.
IEICE Trans. Commun., 2014
Resource-efficient acquisition architecture for BOC-modulated signals.
IEICE Electron. Express, 2014
Ultra-low power dissipation of improved complementary pass-transistor adiabatic logic circuits based on FinFETs.
Sci. China Inf. Sci., 2014
Low power adiabatic logic based on FinFETs.
Sci. China Inf. Sci., 2014
High-speed constant-time division module for Elliptic Curve Cryptography based on GF(2<sup>m</sup>).
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
A capacitive Interface Circuit with capacitor mismatch Auto-compensation for MEMS gyroscope.
J. Circuits Syst. Comput., 2013
A Low-noise High-voltage Interface Circuit for capacitive MEMS gyroscope.
J. Circuits Syst. Comput., 2013
Design of a Reconfigurable Acoustic Modem for Underwater Sensor Networks.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
A Dynamic-Adjusting Threshold-Voltage Scheme for FinFETs low power designs.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2011
A JTAG-based configuration circuit applied in SerDes chip.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2009
A Low Cost Correlator Structure in the Pseudo-Noise Code Acquisition System.
IEICE Trans. Commun., 2009
Application-Dependent Interconnect Testing of Xilinx FPGAs Based on Line Branches Partitioning.
IEICE Trans. Inf. Syst., 2009
2006
An Efficient VLSI Implementation of Distributed Architecture for DWT.
Proceedings of the IEEE 8th Workshop on Multimedia Signal Processing, 2006
A Discrete STFT Processor for Real-time Spectrum Analysis.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
A CMOS Differential Difference Amplifier with Reduced Nonlinearity Error of Interpolation for Interpolating ADCs.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
Design and Implementation of a 2-level FSK Digital Modems Using CORDIC Algorithm.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006