2024
Primate: A Framework to Automatically Generate Soft Processors for Network Applications.
IEEE Comput. Archit. Lett., 2024
Beyond Inference: Performance Analysis of DNN Server Overheads for Computer Vision.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
PEARL: Enabling Portable, Productive, and High-Performance Deep Reinforcement Learning using Heterogeneous Platforms.
Proceedings of the 21st ACM International Conference on Computing Frontiers, 2024
2023
A Software-Hardware Co-Optimized Toolkit for Deep Reinforcement Learning on Heterogeneous Platforms.
CoRR, 2023
2016
Proceedings of the FPGAs for Software Programmers, 2016
2015
High-Level Design Tools for Floating Point FPGAs.
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015
2014
Gzip on a chip: high performance lossless data compression on FPGAs using OpenCL.
Proceedings of the International Workshop on OpenCL, 2014
2013
Profile-guided floating- to fixed-point conversion for hybrid FPGA-processor applications.
ACM Trans. Archit. Code Optim., 2013
Harnessing the power of FPGAs using altera's OpenCL compiler.
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013
Fractal video compression in OpenCL: An evaluation of CPUs, GPUs, and FPGAs as acceleration platforms.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
From opencl to high-performance hardware on FPGAS.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
Invited paper: Using OpenCL to evaluate the efficiency of CPUS, GPUS and FPGAS for information filtering.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
2011
Line-level incremental resynthesis techniques for FPGAs.
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011
2010
Parallelizing FPGA Technology Mapping Using Graphics Processing Units (GPUs).
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010
A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010
2007
Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow.
IEEE Trans. Very Large Scale Integr. Syst., 2007
FPGA PLB Architecture Evaluation and Area Optimization Techniques Using Boolean Satisfiability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
An area-efficient timing closure technique for FPGAs using Shannon's expansion.
Integr., 2007
Incremental placement for structured ASICs using the transportation problem.
Proceedings of the IFIP VLSI-SoC 2007, 2007
2006
Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow.
Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006
Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
2005
FPGA Logic Synthesis Using Quantified Boolean Satisfiability.
Proceedings of the Theory and Applications of Satisfiability Testing, 2005
Post-Placement BDD-Based Decomposition for FPGAs.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
FPGA PLB Evaluation using Quantified Boolean Satisfiability.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
Incremental retiming for FPGA physical synthesis.
Proceedings of the 42nd Design Automation Conference, 2005
FPGA technology mapping: a study of optimality.
Proceedings of the 42nd Design Automation Conference, 2005
Two-stage physical synthesis for FPGAs.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2004
The Quartus University Interface Program: enabling advanced FPGA research.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004
2003
Automated Extraction of Physical Hierarchies for Performance Improvement on Programmable Logic Devices.
Proceedings of the International Conference on VLSI, 2003
2002
Incremental placement for layout driven optimizations on FPGAs.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002
Constrained clock shifting for field programmable gate arrays.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002
Integrated retiming and placement for field programmable gate arrays.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002
2001
The case for registered routing switches in field programmable gate arrays.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2001