A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital CDR in 7NM FinFET.
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Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET.
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IEEE J. Solid State Circuits, 2017
6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET.
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Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017