2024
On the Fine Tuning of RRAM Resistance Under Variability Using Current Pulses at SET.
Proceedings of the 30th IEEE International Symposium on On-Line Testing and Robust System Design, 2024
Engineering UGR-VCMTCF RRAM Model for Adjusting to TiN/Ti/HfO2/W Devices.
Proceedings of the 39th Conference on Design of Circuits and Integrated Systems, 2024
2023
True Random Number Generator Based on the Variability of the High Resistance State of RRAMs.
IEEE Access, 2023
2022
On the Fitting and Improvement of RRAM Stanford-Based Model Parameters Using TiN/Ti/HfO2/W Experimental Data.
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022
2021
Simulation of serial RRAM cell based on a Verilog-A compact model.
Proceedings of the XXXVI Conference on Design of Circuits and Integrated Systems, 2021
Low Cost AES Protection Against DPA Using Rolling Codes.
Proceedings of the XXXVI Conference on Design of Circuits and Integrated Systems, 2021
2020
A forming-free ReRAM cell with low operating voltage.
IEICE Electron. Express, 2020
2019
Postbond Test of Through-Silicon Vias With Resistive Open Defects.
IEEE Trans. Very Large Scale Integr. Syst., 2019
2016
Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Prebond Testing of Weak Defects in TSVs.
IEEE Trans. Very Large Scale Integr. Syst., 2016
RRAM based cell for hardware security applications.
Proceedings of the 1st IEEE International Verification and Security Workshop, 2016
2014
Pre-bond testing of weak defects in TSVs.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Post-bond test of Through-Silicon Vias with open defects.
Proceedings of the 19th IEEE European Test Symposium, 2014
2013
Diagnosis of Interconnect Full Open Defects in the Presence of Gate Leakage Currents.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
BIST architecture to detect defects in tsvs during pre-bond testing.
Proceedings of the 18th IEEE European Test Symposium, 2013
2011
Gate Leakage Impact on Full Open Defects in Interconnect Lines.
IEEE Trans. Very Large Scale Integr. Syst., 2011
Diagnosis of Interconnect Full Open Defects in the Presence of Fan-Out.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
2010
Diagnosis of full open defects in interconnect lines with fan-out.
Proceedings of the 15th European Test Symposium, 2010
2009
Delay caused by resistive opens in interconnecting lines.
Integr., 2009
2008
Experimental Characterization of CMOS Interconnect Open Defects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Full Open Defects in Nanometric CMOS.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008
Time-dependent Behaviour of Full Open Defects in Interconnect Lines.
Proceedings of the 2008 IEEE International Test Conference, 2008
2007
Diagnosis of Full Open Defects in Interconnecting Lines.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007
Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007
2005
Defective behaviours of resistive opens in interconnect lines.
Proceedings of the 10th European Test Symposium, 2005
2003
Process-variability aware delay fault testing of ΔV<sub>T</sub> and weak-open defects.
Proceedings of the 8th European Test Workshop, 2003